VHDL

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comp.lang.vhdl
E
Numeric_std.to_unsigned function in VHDL
  • ELI
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0
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194
ELI
E
F
MAX6675 VHDL
  • Francovps1999
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0
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143
Francovps1999
F
A
How does a HEAD pointer end up pointing to the first node in a linked list?
  • Ash72
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3
Views
417
Ash72
A
H
VHDL: AXI-stream FIFO
  • HMSStanley
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2
Views
851
HMSStanley
H
S
New to VHDL... Trying to convert a 2-bytes number into an decimal
  • ST3005
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0
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349
ST3005
S
G
Piotrowski, Walt,
  • God1989
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0
Views
288
God1989
G
L
Reed solomon decoder issue
  • lokeshvayala
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0
Views
301
lokeshvayala
L
B
Clock divide by 5
  • blesssy
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0
Views
385
blesssy
B
Q
How to check time delay caused by code itself?
  • Quuruu
Replies
1
Views
451
Quuruu
Q
H
Some Cash for Vhdl coding
  • Harry12
Replies
0
Views
324
Harry12
H
H
Vhdl coding
  • Harry12
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0
Views
349
Harry12
H
R
Can anyone please help me in this code
  • ragerrani
Replies
1
Views
458
TheAliceMay
T
A
What is `transaction`event
  • Ash72
Replies
0
Views
370
Ash72
A
R
Low level block coding
  • Roger31415
Replies
0
Views
371
Roger31415
R
A
What does 'genbin' and 'addbins' in OSVVM mean?
  • Ash72
Replies
0
Views
394
Ash72
A
D
Binary to BCD code understanding
  • div_01
Replies
0
Views
664
div_01
D
N
Outputting signal values to terminal Within Character Array
  • new_guy_505
Replies
0
Views
683
new_guy_505
N
L
Line 50. parse error, unexpected IDENTIFIER, expecting SEMICOLON
  • Luis7910
Replies
0
Views
961
Luis7910
L
N
VHDL -> 16-bit register with parallel load / shift_R / shift_L / asyncr_reset
  • Nikos_for_vhdl
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0
Views
2K
Nikos_for_vhdl
N
M
VHDL multiplier
  • mk7899
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0
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1K
mk7899
M
K
Register clear on read
  • kamalre
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0
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2K
kamalre
K
X
IC 74374-getting incorrect simulation
  • xorro
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0
Views
1K
xorro
X
D
2 JK Circuit in VHDL
  • dumdumdum
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0
Views
1K
dumdumdum
D
A
Cannot find <math_utility_pkg> in library <ieee_proposed>
  • ADHUL
Replies
0
Views
1K
ADHUL
A
A
sum of a array's element
  • alireza95
Replies
0
Views
1K
alireza95
A
A
reading binary file using vhdl
  • assaad EL Makhloufi
Replies
0
Views
1K
assaad EL Makhloufi
A
J
Sine wave 200khz , having a digital 16 bit value using VHDL
  • JaneJune
Replies
0
Views
1K
JaneJune
J
C
How to get signal name as a string in a procedure?
  • Cor
Replies
0
Views
1K
Cor
C
A
Problem With Mealy Sequence Detector
  • Armand
Replies
1
Views
1K
Cor
C
L
Cannot Read Data in 1-Port RAM IP Core
  • learni
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0
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1K
learni
L
L
LFSR doesn't generate random values during simulation
  • learni
Replies
1
Views
1K
Cor
C
A
How to write if statement written in matlab with vhdl ?
  • afef
Replies
0
Views
1K
afef
A
A
verilog, rtl, simulation
  • akshata@94
Replies
0
Views
1K
akshata@94
A
S
Reading an xml file in vhdl
  • sandeepthi
Replies
0
Views
2K
sandeepthi
S
A
need to count constants names in vhdl
  • Ana
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0
Views
2K
Ana
A
K
Comparing Inputs to Outputs Simon Game
  • KC1
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0
Views
1K
KC1
K
K
Query related to division of 1.122 in mentioned code.
  • Kritika Bhardwaj
Replies
0
Views
1K
Kritika Bhardwaj
K
S
verilog hdl
  • shachi
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0
Views
1K
shachi
S
C
Illegal sequential statement (VHDL)
  • chiraz
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0
Views
2K
chiraz
C
A
conversion from 8bit to 4 bit in vhdl
  • alok das gupta
Replies
1
Views
3K
Cor
C
A
lms algorithm code
  • alok das gupta
Replies
0
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1K
alok das gupta
A
L
Mixer-Unit on Altera DE2-115 Cyclone IV
  • Larinayo
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0
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1K
Larinayo
L
A
VHDL Subtraction two’s complement
  • Alenx
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0
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3K
Alenx
A
Z
Xilinx ISE, expression not globally static inside generic map
  • Zo Ki
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0
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1K
Zo Ki
Z
A
2 flip-flop synchronizer
  • andys86498
Replies
1
Views
3K
netguy63
N
A
How to use ufixed when it involves multiplication a number of times?(VHDL question)
  • Anwesa Roy
Replies
0
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2K
Anwesa Roy
A
R
Input ports in VHDL of type string and Boolean
  • Razn_957
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0
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2K
Razn_957
R
R
Issue with simulation time - Modelsim PE Student 10.4
  • Rashnak
Replies
1
Views
1K
Rashnak
R
miroslavasadov
pls help me ; vhdl;
  • miroslavasadov
Replies
0
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2K
miroslavasadov
miroslavasadov
M
I need a VHDL code
  • Moh
Replies
0
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2K
Moh
M

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