VHDL

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comp.lang.vhdl
R
I'd rather switch than fight!
  • rickman
5 6 7
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127
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6K
radarman
R
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New keyword 'orif' and its implications
  • Weng Tianxiang
4 5 6
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113
Views
5K
Mike Treseler
M
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Hardware book like "Code Complete"?
  • Davy
2 3 4
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73
Views
4K
Tom Lucas
T
A
debounce state diagram FSM
  • Anson.Stuggart
2 3 4
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66
Views
7K
christian.bau
C
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Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
  • Weng Tianxiang
2 3 4
Replies
63
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4K
Weng Tianxiang
W
A
combinational loops
  • alb
2 3
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54
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4K
alb
A
E
Style of coding complex logic (particularly state machines)
  • Eli Bendersky
2 3
Replies
53
Views
4K
Martin Thompson
M
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I hate VHDL!!!
  • Weng Tianxiang
2 3
Replies
51
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7K
roller
R
J
Describing pipelined hardware
  • Jonathan Bromley
2 3
Replies
50
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3K
Ben Jones
B
A
Variable vs. Signal on indexing
  • ALuPin
2 3
Replies
50
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7K
Mike Treseler
M
C
Embedded languages based on early Ada (from "Re: Preferred OS, processor family for running embedded
  • Colin Paul Gloster
2 3
Replies
48
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5K
Colin Paul Gloster
C
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FSM in illegal state
  • Jerker Hammarberg \(DST\)
2 3
Replies
48
Views
5K
Sander Vesik
S
Y
state machine reset
  • yiipee
2 3
Replies
48
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3K
kennheinrich
K
K
Questa AVM
  • knight
2 3
Replies
47
Views
4K
KJ
K
A
Coding style, wait statement, sensitivity list and synthesis.
  • AG
2 3
Replies
45
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12K
Andy
A
A
Version Control for VHDL Project
  • AndreasWallner
2 3
Replies
44
Views
5K
KJ
K
R
Why Doesn't VHDL Have a Wildcard Sensitivity List?
  • rickman
2 3
Replies
42
Views
4K
Mike Treseler
M
P
VHDL language is out of date! Why? I will explain.
  • psihodelia
2 3
Replies
41
Views
3K
MikeShepherd564
M
A
RTL for Z8000 series CPU?
  • ajcrm125
2 3
Replies
40
Views
5K
Tobias Weingartner
T
D
Conditional signal assignment or process statement
  • devas
2 3
Replies
40
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5K
Andy
A
R
Creating new operators
  • rickman
2
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39
Views
2K
rickman
R
D
How to count zeros in registers?
  • Davy
2
Replies
39
Views
12K
Ulf Samuelsson
U
T
How Synopsys could save $$ without offshoring
  • Tom Joad
2
Replies
38
Views
2K
fabbl
F
K
SOS : 4-bit binary divider circuit PLEASE!!!!!!!
  • kpk
2
Replies
37
Views
20K
Bob Stephens
B
N
synthesizing 'rightof or 'succ
  • Neha
2
Replies
37
Views
2K
Andy
A
L
*RANT* Ridiculous EDA software "user license agreements"?
  • license_rant_master
2
Replies
37
Views
3K
marcus.harnisch
M
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Are HDLs Misguided?
  • rickman
2
Replies
37
Views
2K
Paul Colin Gloster
P
E
An implementation of a clean reset signal
  • Eli Bendersky
2
Replies
37
Views
3K
Eli Bendersky
E
A
Sync + FIFO
  • ALuPin
2
Replies
36
Views
4K
Ronald H. Nicholson Jr.
R
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How much time does it need to sort 1 million random 64-bit/32-bit integers?
  • Weng Tianxiang
2
Replies
36
Views
9K
Brannon
B
G
Building Coaxial transmission line on PCB?
  • Geronimo Stempovski
2
Replies
35
Views
3K
glen herrmannsfeldt
G
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How to write testbench file?
  • RaulGonz
2
Replies
35
Views
5K
KJ
K
P
Why hardware designers should switch to Eclipse
  • Philippe
2
Replies
35
Views
3K
Nico Coesel
N
N
Signed, Unsigned syntax issues. Please help, I'm stumped
  • nitrogenocide
2
Replies
35
Views
4K
KJ
K
M
vhdl questions from a verilog person
  • Mark Brehob
2
Replies
35
Views
4K
Tricky
T
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nesting counters
  • john
2
Replies
35
Views
3K
Ralf Hildebrandt
R
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VHDL expert puzzle
  • Jan Decaluwe
2
Replies
35
Views
2K
Bart Fox
B
D
TextIO Tutorial
  • Dek
2
Replies
34
Views
11K
vhdldevelopper
V
J
Best CPU platform(s) for FPGA synthesis
  • jjohnson
2
Replies
33
Views
4K
Guest
G
M
Newbie question on combining if rising_edge(clk).
  • mindentropy
2
Replies
32
Views
2K
KJ
K
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Use of libraries
  • PlayDough
2
Replies
32
Views
4K
Martin Thompson
M
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signals in sensitiv list... and reset
  • Rick North
2
Replies
32
Views
2K
jacko
J
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VHDL and Latch
  • Weng Tianxiang
2
Replies
31
Views
15K
Colin Paul Gloster
C
A
[cross-post]path verification
  • alb
2
Replies
31
Views
2K
HT-Lab
H
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boolean operations on "integer" in VHDL'93
  • whygee
2
Replies
31
Views
7K
Colin Paul Gloster
C
S
Changing refresh rate for DRAM while in operation?
  • sendthis
2
Replies
31
Views
3K
sendthis
S
D
Re: Modelsim PE vs. Aldec Active-HDL (PE)
  • d_s_klein
2
Replies
30
Views
6K
Anssi Saari
A
B
VHDL Coding Style Guide
  • Bert Cuzeau
2
Replies
30
Views
18K
lokesh_boddu
L
J
Quartus II infered latches
  • jacko
2
Replies
30
Views
3K
jacko
J
L
two related process
  • lucianofalbo
2
Replies
29
Views
2K
jeppe
J

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