VHDL

Post thread
comp.lang.vhdl
M
Design is too large for the device! xc3s400
  • methi
2
Replies
29
Views
2K
glen herrmannsfeldt
G
M
INOUT port on entity
  • minkowsky
2
Replies
29
Views
2K
Jos De Laender
J
P
"Global Variables" for configuration in VHDL
  • pvwa
2
Replies
27
Views
8K
Tricky
T
Z
shift_right/ shift_left
  • ZHIQUAN
2
Replies
27
Views
21K
Mike Treseler
M
W
Which is the most beautiful and memorable hardware structure in aCPU?
  • Weng Tianxiang
2
Replies
27
Views
2K
Tim McCaffrey
T
R
Dual Port RAM Inference
  • rickman
2
Replies
27
Views
14K
rickman
R
W
Null statement in VHDL
  • Weng Tianxiang
2
Replies
26
Views
2K
Andy
A
T
More synthesis myths?
  • Tricky
2
Replies
26
Views
2K
JimLewis
J
H
VHDL language of choice?
  • Herb T
2
Replies
26
Views
3K
Jim Lewis
J
V
How to write a VHDL code for 1Hz signal?
  • Vagant
2
Replies
25
Views
7K
kennheinrich
K
J
Fast Counter
  • Jessica Shaw
2
Replies
25
Views
4K
John Kent
J
S
uninferred due to asynchronous read logic
  • Shannon
2
Replies
25
Views
6K
Shannon
S
B
Is anyone aware of a VHDL dependency finder?
  • bwilson79
2
Replies
25
Views
3K
Mike Treseler
M
E
Exportability of EDA industry from North America?
  • EDA wannabe
2
Replies
25
Views
2K
Tobias Weingartner
T
M
Questions about single process coding style
  • Mike Treseler
2
Replies
24
Views
3K
Mike Treseler
M
J
alternate synchronous process template
  • jens
2
Replies
24
Views
2K
mtreseler
M
A
Using unregistered inputs in FSM
  • ALuPin
2
Replies
24
Views
2K
Mike Treseler
M
L
Squaring of a binary number
  • lokesh kumar
2
Replies
24
Views
2K
lokesh kumar
L
L
Overflow on INTEGER value.
  • Luis Cupido
2
Replies
24
Views
5K
Luis Cupido
L
B
When are two clock domains actually considered asynchronous?
  • Beppe
2
Replies
24
Views
5K
rickman
R
A
State Machine with single cycle pulsed outputs?
  • Analog_Guy
2
Replies
24
Views
2K
m
M
W
ieee.numeric_std?
  • Weng Tianxiang
2
Replies
24
Views
9K
janeruth
J
W
How a state machine is constructed using latches?
  • Weng Tianxiang
2
Replies
23
Views
3K
Weng Tianxiang
W
S
which commercial HDL-Simulator for FPGA?
  • SynopsysFPGAexpress
2
Replies
23
Views
3K
SynopsysFPGAexpress
S
H
Synthesis wrapper
  • hssig
2
Replies
23
Views
2K
Mike Treseler
M
R
News on VHDL-200X
  • Rick North
2
Replies
23
Views
2K
Hans
H
M
VHDL and Emacs (My experience)
  • mans
2
Replies
23
Views
8K
Mike Treseler
M
W
Mixed clocked/combinatorial coding styles (another thread)
  • whygee
2
Replies
23
Views
3K
Mike Treseler
M
R
The littlest CPU
  • rickman
2
Replies
23
Views
3K
Frank Buss
F
S
stumped on syntax yet again!
  • Shannon
2
Replies
22
Views
4K
Rob Dekker
R
M
Request for feedback: proposed new Perl modules to aid VHDL projects
  • Michael Attenborough
2
Replies
22
Views
4K
Mike Treseler
M
V
vhdl for beginners
  • vipin lal
2
Replies
22
Views
6K
Rajmathi
R
A
Gray counter
  • ast
2
Replies
22
Views
12K
omahens
O
A
timing verification
  • alb
2
Replies
22
Views
2K
Mike Treseler
M
T
What FSM should I use ?
  • Thor Phersen
2
Replies
22
Views
4K
Jan Decaluwe
J
Y
RFC on VHDL LRM 93[8.4.1]
  • yaveh (Yet Another Vhdl Engineer Hoping)
2
Replies
22
Views
2K
Andy
A
T
Design toplevel module as schematic?
  • Tobias Baumann
2
Replies
22
Views
3K
Anssi Saari
A
S
Signal in a Case Statement
  • Shannon
2
Replies
22
Views
2K
Paul Uiterlinden
P
G
Division of an integer by a real number using VHDL
  • genlock
2
Replies
22
Views
36K
vipinlal
V
R
Dual data rate in Xilinx WebPACK 7.1
  • Rafal Pietrak
2
Replies
22
Views
2K
Mike Treseler
M
S
VHDL Fixed Point package...
  • Sergey Katsev
2
Replies
22
Views
11K
kashyap.12
K
M
Electrical gigabit transmission ?
  • Michael Weiss
2
Replies
22
Views
2K
Rob Warnock
R
A
TCL CODE WITH VHDL
  • AAA
2
Replies
22
Views
8K
AAA
A
W
How to get lowest price for a ModelSim license?
  • Weng Tianxiang
2
Replies
21
Views
31K
ngsayjoe
N
E
Coding complex VHDL testbenches
  • Eli Bendersky
2
Replies
21
Views
6K
Jonathan Bromley
J
C
VHDL refactoring tools
  • c d saunter
2
Replies
21
Views
2K
Mike Treseler
M
S
std_logic_vector signals in sensitivity list process
  • Steven Kauffmann
2
Replies
21
Views
10K
Ponceludon de Malavoy
P
M
ISE 9.2.03i problem
  • Mark McDougall
2
Replies
21
Views
2K
Mark McDougall
M
S
Version control for VHDL projects.
  • Symon
2
Replies
21
Views
5K
KJ
K
V
Identity-conversion of the clock signal
  • valentin tihhomirov
2
Replies
21
Views
3K
Andy
A

Members online

Total: 22 (members: 1, guests: 21)
Robots: 352

Forum statistics

Threads
473,755
Messages
2,569,536
Members
45,014
Latest member
BiancaFix3

Latest Threads

Top