VHDL

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comp.lang.vhdl
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newbie: integer to bit_vector
  • =?ISO-8859-1?Q?Sch=FCle_Daniel?=
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5
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=?ISO-8859-1?Q?Sch=FCle_Daniel?=
?
J
while loop
  • jiten
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17
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Andy Peters
A
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SOS : 4-bit binary divider circuit PLEASE!!!!!!!
  • kpk
2
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37
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Bob Stephens
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time quantity in vhdl
  • Nav
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3
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Nav
N
C
SRL and ROL
  • Chris Connelly
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3
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Mike Treseler
M
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converting floating point to fixed point
  • H aka N
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15
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Ben Jones
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VHDL -> block diagram
  • dave.bryan
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18
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JohnDuq
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Bidirectional Port Usage in VHDL?
  • Pino
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7
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20K
Nicolas Matringe
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D
How to access individual bits of std_logic_vector
  • Daku
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6
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20K
Daku
D
D
VHDL VGA controller
  • dashdingo
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3
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19K
jpk216
J
G
MOD operator
  • Guilherme Corrêa
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4
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19K
Andy
A
J
Coverting WAV file to ASCII
  • jahaya
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4
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19K
Jonathan Bromley
J
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boolean to std_logic
  • valentin tihomirov
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3
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19K
Mike Treseler
M
A
ModelSim - vcom dependency order
  • andyesquire
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17
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19K
Tim Hubberstey
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if-then vs. if-generate
  • valentin tihomirov
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3
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19K
electronics gyan`
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How to find the ABS of std_logic_vector
  • priya
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3
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Andy
A
A
STD_LOGIC_VECTOR >> NATURAL ?
  • aleksa
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9
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19K
Mike Treseler
M
H
Procedure VHDL
  • hilal
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3
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BernhardF
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M
rom in vhdl
  • Mohammed khader
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5
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rickman
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Illegal concurrent statement
  • Massi
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3
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jetq88
J
A
Memory Initialization Files in Modelsim
  • ALuPin
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5
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19K
Nitsan vardi
N
M
Reading hex data from file
  • magik
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6
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19K
Bert Cuzeau
B
A
VHDL Eclipse Plugin
  • andywagner3
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2
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19K
andy.wagner2
A
A
multiplying std logic vectors
  • abilashreddyg
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8
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18K
Nicolas Matringe
N
V
rounding to integer
  • valentin tihomirov
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2
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18K
Jonathan Bromley
J
S
Converting C to VHDL
  • sarath1111
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11
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18K
Bill McCulley
B
R
VHDL and .txt
  • Ronny Hengst
Replies
5
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18K
Jim Lewis
J
A
Constant conversion (natural to std_logic_vector)
  • a1_nocrap_exh
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10
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18K
Andy
A
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newbe: how to print integer and real numbers?
  • =?ISO-8859-1?Q?Sch=FCle_Daniel?=
Replies
4
Views
18K
=?ISO-8859-1?Q?Sch=FCle_Daniel?=
?
A
10327: can't determine definition of operator ""=""
  • artvandelay
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3
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18K
joris
J
P
bit vector to std_logic conversion query
  • pavithrashinde
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1
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18K
Ralf Hildebrandt
R
R
Bad synchronous description, but why ?
  • Roman Himmes
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8
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18K
Duane Clark
D
A
VHDL--usage of WAIT statement in PROCESS
  • anil
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2
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18K
vipinlal
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C
Integer left shift operation
  • cltsaig
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4
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18K
rickman
R
B
VHDL Coding Style Guide
  • Bert Cuzeau
2
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30
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18K
lokesh_boddu
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VCD file format
  • Neil Zanella
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3
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17K
toxic_iguana
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SR Flip Flop
  • RishiD
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2
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17K
Ralf Hildebrandt
R
S
Signal Generator using FPGA and DAC
  • Sheetal
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13
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17K
Geethu
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J
Block Diagram Viewer / Hierarchy Parser for VHDL/Verilog?
  • jjohnson
Replies
5
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17K
Jahagirdar Vijayvithal S
J
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Converting integer to std_logic_vector
  • Rockerboy
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5
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17K
Andy
A
E
force signals in VHDL
  • esperan
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3
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17K
esperan
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ASIC gate count estimation
  • nmatringe
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11
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17K
Nikolaos Kavvadias
N
M
clock divider by 2
  • martstev
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3
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17K
arant
A
Q
Multiplier
  • Quinnie
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4
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17K
Ralf Hildebrandt
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X
ADC and DAC Converters VHDL model
  • Xabier Iturbe
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6
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17K
rtl.engineer
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Tutorial on writing testbench files
  • Stephane ACOUNIS
Replies
7
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17K
QuestaTechnologies
Q
M
std_logic vs bit
  • Mohammed A.khader
Replies
11
Views
17K
Jim Lewis
J
S
Converting std_logic_vector to integer
  • skilambi
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3
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17K
David Binnie
D
H
declaring real numbers (2^15-1) and (-2^15) in vhdl
  • hari
Replies
2
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17K
Charles Bailey
C
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VHDL and signed numbers
  • salman sheikh
Replies
3
Views
16K
John LeVieux
J

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