VHDL

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comp.lang.vhdl
W
About Altera patent application "Logic Cell Supporting Addition ofThree Binary Words"
  • Weng Tianxiang
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17
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1K
Weng Tianxiang
W
M
using procedures
  • Michel Bieleveld
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17
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1K
Jeroen
J
J
while loop
  • jiten
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17
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20K
Andy Peters
A
G
one signal set ffrom two processes .....
  • Gerhard
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17
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3K
Alessandro Basili
A
A
compact bus description
  • alb
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17
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1K
alb
A
T
ANNOUNCE: TimingAnalyzer version beta 0.87
  • timinganalyzer
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17
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1K
rickman
R
M
Generic shift register where value 'n' keeps changing
  • methi
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16
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5K
Martin Thompson
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A
Xilinx ISE 8.1i Trouble
  • Alex
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16
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6K
Alex
A
N
CASE statement & LOOP
  • Niv
Replies
16
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7K
Niv
N
M
GNU Lesser Public License and Soft IP
  • moogyd
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16
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3K
Paul Uiterlinden
P
A
concurrent assertion statement and delta races
  • Allan Herriman
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16
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2K
Allan Herriman
A
D
Scoreboard and Checker in Testbench?
  • Davy
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16
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9K
pini
P
E
Some text processing questions
  • Eli Bendersky
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16
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1K
M. Hamed
M
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noob question on loops
  • Karol Hennessy
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16
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1K
rickman
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V
assignment with *when* statement
  • Valentin Tihomirov
Replies
16
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2K
fe
F
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Unassigned register decode
  • trescot
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16
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1K
Amal
A
A
data enable on a FF
  • Al
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16
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1K
lokesh_boddu
L
N
SR Flip Flop
  • Nirav
Replies
16
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2K
Mike Treseler
M
D
problem with a shift register
  • dauzat.lilian
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16
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2K
Mike Treseler
M
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BIT, STD_LOGIC,STD_ULOGIC
  • RealInfo
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16
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5K
beky4kr
B
B
2 counters, counting states of Bit stream
  • brandon.spiteri
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16
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2K
Andy
A
L
millions combinations of test vectors for ALU
  • Lily
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16
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2K
Bob Jenkins
B
A
Count bits in VHDL, with loop and unrolled loop produces different results
  • a s
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16
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6K
JustJohn
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S
ANN: Introducing MANIK - a 32 bit Soft-Core RISC Processor
  • Sandeep Dutta
Replies
16
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2K
Walter Banks
W
S
Checksum comparisons
  • Shannon
Replies
16
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1K
KJ
K
J
Beginner question: What trigs processes
  • Jerker Hammarberg
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16
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2K
Mike Treseler
M
P
Shift register extraction fails
  • Philip Herzog
Replies
16
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2K
Symon
S
N
Register with a default Value
  • Nemesis
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16
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7K
Ken Cecka
K
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Help: what does this VHDL code mean?
  • Pratip Mukherjee
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16
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2K
Kim Enkovaara
K
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FF with CE doesn't synthesize correctly by XST?
  • MM
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16
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1K
MM
M
N
Version Control Software
  • Neill A
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16
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5K
Duane Clark
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integer type output signal is synthesizable?
  • sonny
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16
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1K
Paul Uiterlinden
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Cannot find function "TO_INTEGER" for these actuals
  • Travis
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16
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2K
Andy
A
A
Dividing by 48
  • ALuPin
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16
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1K
ALuPin
A
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Where are Huffman encoding applications?
  • Weng Tianxiang
Replies
16
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10K
Weng Tianxiang
W
N
redundant signals in sensitivity list?
  • Neil Zanella
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15
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2K
Jim Wu
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N
2 digit dice (random counter 1 - 6)
  • Nathan Osborne
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15
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1K
njozzy
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Did VHDL-2008 get lost ?
  • hssig
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15
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6K
Chris Higgs
C
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Good free or paid merge software that edits two similar files?
  • Weng Tianxiang
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15
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2K
charles.elias
C
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Resolution func in the initialization
  • valtih1978
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15
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1K
Paul Uiterlinden
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S
why systemc?
  • singh.shailendra
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15
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6K
lqicjhgv
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VHDL division
  • vhdl_danne
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15
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3K
KJ
K
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ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
  • timinganalyzer
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15
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3K
Jack
J
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Error "Unsupported Clock Statement" when asigning a value to a signal
  • Georg Gläser
Replies
15
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7K
JohnDuq
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F
quick question
  • FP
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15
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934
rickman
R
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process
  • u_stadler
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15
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1K
Rob Dekker
R
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driving "external" signals from a procedure
  • Eli Bendersky
Replies
15
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11K
Jonathan Bromley
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Complex testbench design strategy
  • Eli Bendersky
Replies
15
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2K
Mike Treseler
M
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Optimizing an inferred counter
  • Marty Ryba
Replies
15
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2K
Martin Thompson
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GPS : Basic pseudo-distance computation
  • le Cl?
Replies
15
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4K
Michel
M

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