VHDL

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comp.lang.vhdl
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Newbie question on combining if rising_edge(clk).
  • mindentropy
2
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32
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2K
KJ
K
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structured VHDL
  • alb
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11
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1K
Andy
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Webinar: VHDL Intelligent Coverage using Open Source VHDLVerification Methodology (OSVVM), July 18
  • Jim Lewis
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0
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Jim Lewis
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The lookup table length is wrong in this description?
  • fl
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0
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726
fl
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need help to design a VHDL code from an algorithm
  • lokesh kumar
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0
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858
lokesh kumar
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S
New VHDL Project
  • shankarmishra124
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3
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832
bknpk
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Need help to design n bit Galois field multiplier
  • lokesh kumar
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0
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1K
lokesh kumar
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counting number of reports in the message window within Modelsim
  • G buf thing
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3
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859
HT-Lab
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VHDL, Big RGB-generator - needs shortening, algorithms
  • rik.wilmer
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3
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839
HT-Lab
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VHDL to CMOS
  • o pere o
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7
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1K
Theo Markettos
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[long] look up table for procedure call
  • alb
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2
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949
alb
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T
Multiple Clocks on single bus
  • TheHogs88
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6
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906
TheHogs88
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How can I design Galois field 2^m multiplier.
  • lokesh kumar
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4
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1K
lokesh kumar
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Distributed Ram with Initial Values (Virtex)
  • Travis
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11
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1K
Andy
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T
signal ram: ram_t := (others => (others '0'));
  • Travis
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3
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2K
Andy
A
P
Ask about finding maximum and second's maximum number in array is given.
  • phanhuyich
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4
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2K
Andy
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R
Chasing Bugs in the Fog
  • rickman
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3
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1K
Nicolas Matringe
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How can I avoid variable in this loop (outside the process)?
  • troll greenЪ
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5
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764
Paul Uiterlinden
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Cannot find function "TO_INTEGER" for these actuals
  • Travis
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16
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2K
Andy
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[ANN] LOOPGEN-Fast hardware looping VHDL IPs
  • Nikolaos Kavvadias
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0
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1K
Nikolaos Kavvadias
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E
DSP48 in synchronous process or not, what's the difference?
  • Ethan Zheng
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2
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792
goouse99
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A
vmkr segmentation fault
  • alb
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1
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842
Paul Uiterlinden
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D
ram problem
  • dwi jayanto Wibowo
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2
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920
Andy
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B
Synchronous programmable counter
  • Brandon Spiteri
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1
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2K
Nicolas Matringe
N
N
How do measure Power,Delay and area in vhdl
  • Noura
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0
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864
Noura
N
B
2 counters, counting states of Bit stream
  • brandon.spiteri
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16
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2K
Andy
A
A
HELP! VHDL real TYPE produces infinite decimal. How to approximateor reduce precision?
  • adam.kimura
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3
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1K
adam.kimura
A
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get accustomed with vhdl 2008
  • Ishaan Wadhwa
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2
Views
894
valtih1978
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A few question about vhdl(clk,signal,etc..)
  • natiben27
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3
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908
Andy
A
B
vhdl-mode emacs - what does creating a Project do?
  • BlackHelicopter
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1
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1K
BlackHelicopter
B
C
Calculating Pulse per minute in a FPGA
  • Cory Shol
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6
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1K
chrisabele
C
S
train ticket machine help needed!
  • sicazoR
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0
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1K
sicazoR
S
V
Cascading the attributes
  • valtih1978
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5
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737
Andy
A
D
implementation of traffic light...
  • danddad61
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5
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1K
rickman
R
I
abstract type signal
  • Ilya Kalistru
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3
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785
kevin.neilson
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Signal xx cannot be synthesized, bad synchronous description error
  • robbevt
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15
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3K
robbevt
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Displaying a 4-digit integer number on 7-segments
  • tudorc11
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0
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2K
tudorc11
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Asynchronous With Select and When Else Statements
  • Cory Shol
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6
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1K
rickman
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B
Counting number of asserted register bits in VHDL
  • bucketonuts
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12
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2K
Andy
A
R
Generics, packages, and VHDL-2008
  • Rob Gaddi
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5
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1K
Rob Gaddi
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VHDL Standards Invitation and Status
  • Jim Lewis
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3
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1K
Jim Lewis
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verification strategy with no specs
  • alb
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4
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851
Rob Anderson
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J
VHDL Model for a MIPS Processor
  • jdavis7667
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1
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1K
Andy
A
A
clocked process and sensitivity list
  • alb
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19
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2K
Andy
A
V
write(output, string)
  • valtih1978
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0
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788
valtih1978
V
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conv_integer
  • geeta k
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1
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1K
[email protected]
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P
Design entry poll: which is your favorite editor?
  • Philippe
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1
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770
alb
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CFP - High-level synthesis - Methodologies and Practice
  • Nikolaos Kavvadias
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0
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1K
Nikolaos Kavvadias
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Compiling error... not sure how to address the errors
  • Zak Asaad
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5
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1K
Zak Asaad
Z
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Dual Edged Counter
  • Cory Shol
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6
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1K
rickman
R

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