VHDL

comp.lang.vhdl

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Carry Save Adder (CSA) Verilog code

humble_Stuff
Nov 13, 2006

Replies: 3

Views: 14K

Nov 25, 2013

alb

A

S

Using Altera LPM megafunctions in Quartus II and VHDL in general

Shannon
Aug 18, 2006

2

Replies: 20

Views: 14K

Aug 25, 2006

fp

F

S

Pulse stretching

Shannon
Feb 7, 2007

Replies: 18

Views: 14K

Feb 15, 2007

asicbaba

A

S

Warning of Xst:2677

Sudeep Vhdl-Rookie
Apr 11, 2007

Replies: 3

Views: 14K

Mar 11, 2010

vipinlal

V

A

real to time

Attila Csosz
Apr 28, 2006

Replies: 2

Views: 14K

Apr 28, 2006

Brian Drummond

B

P

the textio lib and std_logic_textio

Pedro Claro
Jul 25, 2003

Replies: 3

Views: 14K

Jul 28, 2003

Mike Treseler

M

M

numeric_std vs std_logic_arith/unsigned?

Mark Norton
May 15, 2006

Replies: 12

Views: 14K

May 17, 2006

KJ

K

V

what is the problem with latch inference?

VHDL Guy
Sep 28, 2006

Replies: 9

Views: 14K

Oct 2, 2006

fp

F

B

synthesizable MOD operator

Basel Naamna
May 13, 2004

Replies: 2

Views: 14K

May 14, 2004

Ralfe Cookson

R

R

A good way to encode a 1024 one-hot vector into binary?

Ryan
Jan 27, 2005

Replies: 9

Views: 14K

Jan 31, 2005

Ryan

R

K

Case choice must be a locally static expression.

Kenneth Johansson
May 4, 2005

Replies: 9

Views: 14K

May 9, 2005

Mike Treseler

M

A

Expanding Integer Range in VHDL

Andy
Mar 3, 2010

Replies: 7

Views: 14K

Mar 4, 2010

Andy

A

K

Questions about Async FIFO

kedarpapte
Jan 13, 2006

Replies: 1

Views: 14K

Jan 15, 2006

hdlcohen

H

F

conv_std_logic vector

foaud167
Dec 3, 2005

Replies: 2

Views: 14K

Dec 6, 2005

Jim Lewis

J

F

VHDL model of a push button debouncer

fpgawizz
Mar 17, 2005

Replies: 4

Views: 14K

Mar 20, 2005

Winfried Salomon

W

R

making a glitch filter

rajan
Mar 8, 2005

Replies: 2

Views: 14K

Mar 13, 2005

Ulf Samuelsson

U

A

Re: Adding internal signals in Modelsim

Al
Nov 11, 2006

Replies: 4

Views: 14K

Nov 13, 2006

Al

A

V

How to model a buffer in VHDL

vishallko31
Apr 5, 2006

Replies: 6

Views: 13K

May 5, 2006

KJ

K

N

Re: unused wires and VHDL architectures

Neil Zanella
Oct 26, 2003

Replies: 1

Views: 13K

Oct 27, 2003

David R Brooks

D

J

Sensitivity list

John Monro
Jun 17, 2005

Replies: 6

Views: 13K

Jun 17, 2005

Marcus Harnisch

M

A

VHDL code for a microprocessor

abhishek jain
Jan 31, 2004

Replies: 5

Views: 13K

Feb 4, 2004

Jonathan Bromley

J

W

Conditional signal declaration

Willem Oosthuizen
Jul 16, 2003

Replies: 5

Views: 13K

Jul 17, 2003

Mario Trams

M

P

Creating a delay with VHDL without using wait (n00b)

pat_jakubowski
Nov 23, 2006

Replies: 3

Views: 13K

Mar 4, 2010

vipinlal

V

A

VHDL-2002 vs VHDL-93 vs VHDL-87?

afd
Mar 22, 2007

Replies: 1

Views: 13K

Mar 23, 2007

Colin Paul Gloster

C

N

delays: inertial delays vs. transport delays

Neil Zanella
Oct 16, 2003

Replies: 2

Views: 13K

Oct 20, 2003

Niv

N

B

Multiplication in VHDL

b2386
Mar 20, 2009

Replies: 3

Views: 13K

Mar 20, 2009

JohnDuq

J

R

CRC Error CORRECTION

reddy
Apr 21, 2004

Replies: 14

Views: 13K

Mar 3, 2010

fauji86

F

Z

type/subtype definition in entity

zhangpei
Apr 17, 2007

Replies: 3

Views: 13K

Apr 18, 2007

zhangpei

Z

M

how to do a 1 to 4 demultiplexer in vhdl?

MNQ
Jun 26, 2003

Replies: 2

Views: 13K

Aug 14, 2009

pravin.vhdl

P

F

downto vs. to

Fabian
Aug 29, 2007

Replies: 4

Views: 13K

Aug 31, 2007

Brad Smallridge

B

M

Flip-flop delay in VHDL

Marty
Nov 16, 2004

Replies: 13

Views: 13K

Aug 23, 2007

ayza1505

A

M

"global" signal in VHDL

manu
Mar 2, 2006

Replies: 7

Views: 13K

Mar 8, 2006

Barry Brown

B

P

MODELSIM : library generation and mapping

Pasacco
May 24, 2007

Replies: 4

Views: 13K

May 24, 2007

Duane Clark

D

E

Parity Check

Ed
Sep 30, 2004

Replies: 18

Views: 13K

Oct 6, 2009

yassen

Y

S

dummy projects in VHDL/Verilog

shumon
Sep 24, 2003

Replies: 1

Views: 13K

Sep 24, 2003

Jim Wu

J

M

verilog 'pullup' and VHDL

Mark McDougall
Oct 26, 2006

Replies: 5

Views: 13K

Oct 26, 2006

KJ

K

S

model sim errors in my design

srinukasam
Jul 4, 2005

Replies: 1

Views: 13K

Jul 4, 2005

Ralf Hildebrandt

R

G

INOUT std_logic problem in ModelSim

GDan
Jun 4, 2006

Replies: 11

Views: 13K

Jun 29, 2006

violet

V

S

VHDL Goto statement ?

Skybuck Flying
Aug 8, 2005

Replies: 9

Views: 13K

Aug 26, 2005

ajahn

A

?

determining of the position of the MSB

=?ISO-8859-1?Q?Johan_Bernsp=E5ng?=
Jul 27, 2004

2

Replies: 20

Views: 13K

Aug 2, 2004

Jonathan Bromley

J

M

Synthesizable?

Moikel
Oct 20, 2006

Replies: 3

Views: 13K

Oct 20, 2006

Nicolas Matringe

N

P

verification vs validation

pradeep
Nov 21, 2003

Replies: 7

Views: 13K

Nov 25, 2003

Thomas Stanka

T

B

FSM in VHDL

Bigyellow
May 12, 2005

Replies: 8

Views: 13K

May 29, 2010

psycoclan1

P

L

About counter in VHDL

laura_pretty05
Apr 25, 2006

Replies: 6

Views: 13K

Oct 10, 2006

nysopramo

N

M

Viewing variables within process scoped procedures (Modelsim)

Mark
Nov 8, 2004

Replies: 4

Views: 13K

Nov 9, 2004

mike_treseler

M

D

ModelSim & Multithreading

Dek
May 7, 2009

Replies: 7

Views: 13K

May 12, 2009

Marcus Harnisch

M

E

4-phase vs. 2-phase handshaking

Eli Bendersky
Jan 21, 2008

Replies: 11

Views: 12K

Jan 22, 2008

KJ

K

T

Warning: Output pins are stuck at VCC or GND

TheRain
May 13, 2005

Replies: 4

Views: 12K

May 16, 2005

Neo

N

P

Negative setup and Negative hold

prem_eda
Oct 11, 2004

Replies: 5

Views: 12K

Oct 11, 2004

Pieter Hulshoff

P

M

Code Coverage in ModelSim

Matthias Alles
Jun 24, 2009

Replies: 13

Views: 12K

Jun 26, 2009

NigelE

N

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