Recent content by cmelias

  1. C

    VHDL program error

    I don't think you have tried very hard to analyze these errors. The error messages are quite clear. Type of MISO is std_logic_vector; type of s is numeric_std--these types are incompatible. Either change the type of s or use type casting on one of the signals to make the assignment work. You...
  2. C

    problem executing testbench. error in coding

    Your testbench has problems; try this: LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY rom_tb IS END rom_tb; ARCHITECTURE behavior OF rom_tb IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT rom PORT( clk : IN std_logic; address : IN integer...
  3. C

    VHDL

    Look at this Link:https://www.doulos.com/knowhow/vhdl_designers_guide/tips/avoid_synthesizing_unwanted_latches/ There are many other articles on this subject. My problem with this has been if statements that do not have a final else to cover the possible other condition not covered by the...
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