Ok, I seemed to have fixed this issue with supposedly proper handshaking signals where addrA tells port A to stop collecting when it is at its...
I have a dual port RAM (both ports 8 x 31250) and I would like to send data stored in each address of Port B via a UART (RS232).
Here is a...
if a > b then
bitout <= '1';
elsif a < b then
bitout <= '0';
-- disregard bitout
I have a few sets of values...
For me, I'd make a top module that houses the various relevant codes together, connecting those codes through its signal.
So say you have a.vhd...
work <= work_reg;
if a = '1' then
if e = '1' then
if s = '1' then
work_reg <= try_it_out_1st;
It's Halloween in here where ghosts roam...Woooo~~
Let's say we have a signal as such, so I have a sig_reg to make a delay of the signal by half clock cycle.
And using this code:
Hmm, no help?
After much digging around, I need to interface with a microcontroller on the FPGA to write to RAM (DRAM I presume?).
I have zero clue on writing bits onto a RAM (assuming the code is synthesizable). I'm talking about the physical RAM on the FPGA (let's start with...
as in the process will not proceed until a signal changes? are we talking about one or three signals?
personally I don't like using wait...
good day good night
Separate names with a comma.