Ok, I seemed to have fixed this issue with supposedly proper handshaking signals where addrA tells port A to stop collecting when it is at its...
I have a dual port RAM (both ports 8 x 31250) and I would like to send data stored in each address of Port B via a UART (RS232).
Here is a...
if a > b then
bitout <= '1';
elsif a < b then
bitout <= '0';
-- disregard bitout
I have a few sets of values...
For me, I'd make a top module that houses the various relevant codes together, connecting those codes through its signal.
So say you have a.vhd...
work <= work_reg;
if a = '1' then
if e = '1' then
if s = '1' then
work_reg <= try_it_out_1st;
It's Halloween in here where ghosts roam...Woooo~~
Let's say we have a signal as such, so I have a sig_reg to make a delay of the signal by half clock cycle.
And using this code:
Hmm, no help?
After much digging around, I need to interface with a microcontroller on the FPGA to write to RAM (DRAM I presume?).
I have zero clue on writing bits onto a RAM (assuming the code is synthesizable). I'm talking about the physical RAM on the FPGA (let's start with...
as in the process will not proceed until a signal changes? are we talking about one or three signals?
personally I don't like using wait...
good day good night
So I generated some std_logic bits for bitout(i). I had something like
if b(i-1) > "0100" then
bitout(i) <= '0';
elsif b(i-1) < "0100" then...
So I needed to declare a package within the code and the testbench that will allow me to have an array of std_logic_vector's. So 1) is...
Alrighty. State machines don't seem to churn out my output well, ie. not churning out...
But I managed to come out with this easier code (though...
What is the difference between
sig : process
Does CLk : process exist?
I declared the library as such:
I'm a little lost. So you're saying that while the clock is ticking, when the signal is '0', the counter will not move until signal...
yes it is. is there a requirement to state an upper limit for the counter to stop and reset, because the upper limit cycle counts is...
im trying to create counter where it counts the number of cycles upon receiving the first signal, stops the count on receiving the second...
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