a problem about VHDL programming puzzles me

Discussion in 'VHDL' started by hezhang, Feb 14, 2006.

  1. hezhang

    hezhang Guest

    My implementation needs N block RAMs, where N is not a constant, but
    rather a variable.
    That is, if N=5, then only 5 block RAMs are needed; but if N=20, then
    20 block RAMs needed.
    I want to manage these block RAMs and the signals connected with them
    dynamically. That means, every time I changed N, no change is needed to
    change the VHDL source code. Like C/C++, we can allocate mem[N][K],
    then we can access to mem[j] flexibly. How can I do in VHDL?
    Is anyone who can help me?
    Thank you
     
    hezhang, Feb 14, 2006
    #1
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  2. Do one design for the worst case.

    If that doesn't fit, you can
    save multiple designs in flash
    and then have the cpu download
    the one that the user needs to the FPGA.


    -- Mike Treseler
     
    Mike Treseler, Feb 14, 2006
    #2
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  3. I thought by "dynamically," he meant "at compile time" or perhaps "at
    elaboration time." This is known as "locally static" or "globally
    static" in VHDL parlance.

    The result should be easy to achieve using generics.

    Regards,
    Allan
     
    Allan Herriman, Feb 15, 2006
    #3
  4. hezhang

    larthe Guest

    Sounds like a classic case where you would use "generate".

    Regards,
    Lars
     
    larthe, Feb 16, 2006
    #4
  5. dutchgoldtony, Feb 16, 2006
    #5
  6. hezhang

    hezhang Guest

    Thank you for all the above reply!
    Yes, I found "generate" solved the problem. I don't need to allocate
    the max number of block RAMs for the worst case at the begging, but can
    allocate variable number of block RAMs during each synthesis time
    (scalable structure). That is what I want.
     
    hezhang, Feb 16, 2006
    #6
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