a problem about VHDL programming puzzles me

[hezhang]

My implementation needs N block RAMs, where N is not a constant, but
rather a variable.
That is, if N=5, then only 5 block RAMs are needed; but if N=20, then
20 block RAMs needed.
I want to manage these block RAMs and the signals connected with them
dynamically. That means, every time I changed N, no change is needed to
change the VHDL source code. Like C/C++, we can allocate mem[N][K],
then we can access to mem[j] flexibly. How can I do in VHDL?
Is anyone who can help me?
Thank you

 

[Mike Treseler]

I want to manage these block RAMs and the signals connected with them
dynamically. That means, every time I changed N, no change is needed to
change the VHDL source code. Like C/C++, we can allocate mem[N][K],
then we can access to mem[j] flexibly. How can I do in VHDL?

Do one design for the worst case.

If that doesn't fit, you can
save multiple designs in flash
and then have the cpu download
the one that the user needs to the FPGA.


-- Mike Treseler

 

[Allan Herriman]

I want to manage these block RAMs and the signals connected with them
dynamically. That means, every time I changed N, no change is needed to
change the VHDL source code. Like C/C++, we can allocate mem[N][K],
then we can access to mem[j] flexibly. How can I do in VHDL?

Do one design for the worst case.

If that doesn't fit, you can
save multiple designs in flash
and then have the cpu download
the one that the user needs to the FPGA.

I thought by "dynamically," he meant "at compile time" or perhaps "at
elaboration time." This is known as "locally static" or "globally
static" in VHDL parlance.

The result should be easy to achieve using generics.

Regards,
Allan

 

[larthe]

Sounds like a classic case where you would use "generate".

Regards,
Lars

 

[dutchgoldtony]

Yup, generate statement if you want to do it "dynamically". I think
this is what you're after (assuming I read your question right):

http://www.emba.uvm.edu/~jswift/uvm_class/notes/generate.html

Tony
www.tohalloran.co.nr

 

[hezhang]

Thank you for all the above reply!
Yes, I found "generate" solved the problem. I don't need to allocate
the max number of block RAMs for the worst case at the begging, but can
allocate variable number of block RAMs during each synthesis time
(scalable structure). That is what I want.