Adding elements of an array

Discussion in 'VHDL' started by Modukuri, May 29, 2004.

  1. Modukuri

    Modukuri Guest

    Hi:

    I have a 8x8 matrix and I want to add all the 64 elements.I tried
    doing this using two FOR loops,one for row and one for column.It
    didn't work.
    Can anyone suggest a method to do this?

    Thanks,
    Modukuri
     
    Modukuri, May 29, 2004
    #1
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  2. Modukuri

    Jim Lewis Guest

    Create a two dimensional array of type unsigned or
    signed as is appropriate for your problem. Include the
    package:
    use ieee.numeric_std.all ;

    If you still have problems, provide your code and
    so people can point you in the right direction.

    Cheers,
    Jim

    --
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    Jim Lewis
    Director of Training mailto:
    SynthWorks Design Inc. http://www.SynthWorks.com
    1-503-590-4787

    Expert VHDL Training for Hardware Design and Verification
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     
    Jim Lewis, May 30, 2004
    #2
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  3. => 63 additions (quite a lot...)
    First decide, if it is really nessecary to add them in parallel. (->
    Serialized addition; Pipelining?)

    Next, you should think about a tree-based or an array-based adder. The
    simplest form can be described this way:

    sum1<=((a+b) + (c+d)) + ((e+f) + (g+h)); -- tree
    sum2<=(((((((a+b)+c)+d)+e)+f)+g)+h); -- array

    (I did not care for the carry-out (-> overflow).)



    Ralf
     
    Ralf Hildebrandt, May 30, 2004
    #3
  4. Modukuri

    Modukuri Guest

    Hi:

    This is the code,I'm using to sum all the elements of an array.But,at
    the end of simulation,signal "sum" has only the last element of the
    matrix,not the sum of all the 64 elements.I would really appreciate
    any corrections/suggesstions to the code.

    type diff_matrix is array (0 to 7,0 to 7) of integer;
    signal diff : diff_matrix;
    signal sum : integer;

    process(clk,reset)
    begin
    if reset = '1 then
    sum <= 0;
    elsif (clk'event and clk = '1') then
    for i in 0 to 7 loop
    for j in 0 to 7 loop
    sum <= sum_ini + diff(i,j);
    end loop;
    end loop;
    end process;


    Thanks,
    Modukuri
     
    Modukuri, May 30, 2004
    #4
  5. The problem is, that the two loops are actually run through in the
    same simulation cycle, you could think of them being concurrent. So
    every time you assign something to sum, the driver of sum is updated,
    not the signal itself tho. Naturally the last assignment is that of
    the last element of the matrix, which then stays in the driver and is
    assigned to the signal in the next simulation cycle.
    However, the code would work if you used variables instead of signals.
    Something like this maybe:

    type diff_matrix is array (0 to 7,0 to 7) of integer;
    signal diff : diff_matrix;
    signal sum : integer;
    variable temp : integer;

    process(clk,reset)
    begin
    if reset = '1 then
    sum <= 0;
    elsif (clk'event and clk = '1') then
    for i in 0 to 7 loop
    for j in 0 to 7 loop
    temp := temp + diff(i,j);
    end loop;
    end loop;

    sum <= temp
    end if;
    end process;
     
    Christoph M. Wintersteiger, May 30, 2004
    #5
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