adding std_logic_vectors in vhdl

[ohaqqi]

For a command like this one:

C <= std_logic_vector(signed(A) + signed(B))

How does VHDL add the vectors? For example, If I wanted to synthesize this on an FPGA, would the compiler create an adder? Or does it use some other technique to add vectors?
Sorry if this is too much of a newbie question

 

[zty]

i think the synthesis tool will add many adder depend on the length of your vector.

For a command like this one:

C <= std_logic_vector(signed(A) + signed(B))

How does VHDL add the vectors? For example, If I wanted to synthesize this on an FPGA, would the compiler create an adder? Or does it use some other technique to add vectors?
Sorry if this is too much of a newbie question

 

[ohaqqi]

i think the synthesis tool will add many adder depend on the length of your vector.

That makes sense, thanks.

Does it use ripple-carry or carry-look-ahead adders?

 

[Daniel Kho]

Does it use ripple-carry or carry-look-ahead adders?

Different compilers synthesize the same code differently sometimes. I guess you can know how your particular FPGA would implement your code at the RTL level by looking at the RTL viewer if your vendor provides such an option.