Address muxing from multiple sources

Discussion in 'VHDL' started by Salman Sheikh, Aug 28, 2003.

  1. Hello Out there,

    I am trying to come up with an addressing scheme for a memory in my FPGA. I
    have various modules with the my algorithm that need to address the RAM
    memory. My question is this: How is the best way to write the code to
    address the memory from different state address sources. Each address
    source will access the memory sequentially. I thought of a mux where I
    have a controller picking which block addresses the memory and has access
    to the address and data lines, something like this:


    process (sel_192, mem_en_sum, mem_en_exact, addr_exact, addr_colsum,
    mem_en_minmax, addr_minmax, mem_en_estcen, addr_estcent, addrofst0,
    addrofst1, addrofst2, addrofst3, addrofst4)
    case sel_192 is
    when "000" =>
    membank0 <= mem_en_sum & addr_colsum;
    membank1 <= mem_en_sum & addr_colsum;
    membank2 <= mem_en_sum & addr_colsum;
    membank3 <= mem_en_sum & addr_colsum;
    membank4 <= mem_en_sum & addr_colsum;
    when "001" =>
    membank0 <= mem_en_minmax & addr_minmax;
    when "010" =>
    membank0 <= mem_en_estcen & addr_estcent;
    when "011" =>
    membank0 <= mem_en_exact & addr_exact;
    when "100" =>
    membank0 <= '1' & addrofst0;
    membank1 <= '1' & addrofst1;
    membank2 <= '1' & addrofst2;
    membank3 <= '1' & addrofst3;
    membank4 <= '1' & addrofst4;
    when others =>
    membank0 <= (others => 'Z');
    membank1 <= (others => 'Z');
    membank2 <= (others => 'Z');
    membank3 <= (others => 'Z');
    membank4 <= (others => 'Z');
    end case;
    end process;

    Is this a good way to procede or does anyone have any suggestions?

    Thanks in advance.

    Salman Sheikh, Aug 28, 2003
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