Hi everybody
The pinout will be different for one thing.
If your code infers registers, counters, ram etc.,
all you have to do is a synth compile for the new device.
If your code instances registers, counters, ram etc. from
an Altera code generator, it's a redo.
One difference I found was that the Altera block-RAM implementation allowed
async reads while the Xilinx version supported sync reads only. This can
cause truble depending on your desing. If you infer a sync write-async read
RAM in Xilinx it will be implemented in distributed RAM instead of
block-RAMs. I also seem to recall that the Altera FIFO implementation had a
data-counter while the Xilinx version supported only the empty/full flags.
Xilinx FIFOs can't hold the output data indefinitely (due to the sync RAM
read behind the scenes) so you might have to add another layer of
registers/latches, again, depeding on your desing.
Regards,
Andras Tantos
