ANN: SystemVerilog Program Blocks - Project VeriPage Update

Discussion in 'VHDL' started by Swapnajit Mittra, Feb 2, 2005.

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    In this month's article Project VeriPage looks into
    SystemVerilog program block construct which addresses the
    issue of race condition between a design and its test bench.
    It shows you how you can use program blocks to get around
    race conditions to produce a test bench much faster.

    <URL: http://www.project-veripage.com/program_blocks_1.php>

    Project VeriPage has a plethora of articles on Verilog to PL­I
    to SystemVerilog. Here are some:

    o SystemVerilog Structure and Unions:
    <URL: http://www.project-veripage.com/sv_structure.php>

    o SystemVerilog DPI Tutorial:
    <URL: http://www.project-veripage.com/dpi_tutorial_1.php>

    o Little Bit of History (of HDL):
    <URL: http://www.project-veripage.com/history.php>
     
    Swapnajit Mittra, Feb 2, 2005
    #1
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