Are all the signals read in the process should appear in the sensitivity list of the process?

Discussion in 'VHDL' started by walala, Sep 9, 2003.

  1. walala

    walala Guest

    Dear all,

    I have the following questions about sensitivity list of the process:

    1. In the first one, the modelsim simulator says that "Synthesis
    WARNING: count is read in the process but not in the sensitivity
    list"...

    But I read a lot of online tutorials, they do not put count in the
    sensitivity list
    --------------------------------
    p0: PROCESS(rst, clk)
    BEGIN
    if rst = '1' then
    count <= "000";
    elsif (clk'event and clk = '1') then
    count <= count + '1';
    end if;
    END PROCESS p0;

    ---------------------------------


    2. This one is a totally combinatory logic -- a MUX, but do I need to
    put so many signals in my senstivity list? (where count is dertermined
    by the above counter, t1, t2, ... t23 were computed before as
    temporary signals...)

    p1: PROCESS(count, t1, t2, t3, t4, t5, t6, t7, t8, t9, t12, t13,
    t14, t15, t16, t17, t18, t19, t20, t21, t22, t23)
    BEGIN
    case count is
    when "000" =>
    temp1<=t1+t6+t22;
    temp2<=t2+t12;
    temp3<=t3+t13;
    temp4<=t4+t14;
    temp5<=t5+t15;

    when "001" =>
    temp1<=t1+t7+t23;
    temp2<=t2+t13;
    temp3<=t3+t16;
    temp4<=t4+t17;


    ....

    Thanks a lot,

    -Walala
     
    walala, Sep 9, 2003
    #1
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  2. The template from the online tutorial is right and Modelsim is wrong.
    I suggest you turn off the "CheckSynthesis" option in your
    modelsim.ini file, as it results in misleading warnings like this one.


    Yes, you need this many signals in the sensitivity list. Yes, this is
    a PITA (lots of typing for little value, hard to understand, easy to
    make mistakes that describe latches). This feature of the language
    may change in VHDL-200x, and there will be a magic way of indicating
    that all signals on the right hand side of assignment statements are
    automatically in the sensitivity list.
    (Verilog grew a similar feature in its 2001 release, for similar
    reasons.)

    Presumably the signal "temp" is used as an input to a flip flop. In
    this case, you could put all the logic that drives temp inside a
    clocked process, and the sensitivity list would only need to contain
    clock and reset.

    Regards,
    Allan.
     
    Allan Herriman, Sep 9, 2003
    #2
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  3. walala

    walala Guest

    Hi Allan,

    Thank you very much for your posting...

    But I don't understand the comment you made in the last paragraph:
    t1, t2, t3, ..., t23 are computed before the "p1" process:

    t1<=32*X(0);
    t2<=28*X(1);
    ....

    where X(0), X(1), etc. are my inputs...

    The "temp"s are computed after the "p1" process:

    Y(0)<=temp1+temp2;
    Y(1)<=temp1-temp2;
    ....
    where Y(0), Y(1), etc. are my outputs...

    I did not put the assignments to t1, t2, ..., t23s into process and clock
    it; and I also did not put the assignments to Y(0), Y(1), etc. into clocked
    process either...

    I had thought about that: I can put assignments to t's and assignments to
    Y's into clocked processes and also add a "Reset" to the processes...in this
    way all my circuit will be clocked:

    a t-assignment process, a counter process, a "temp"-assignment process based
    on counter, and a final Y-assignment process... all are clocked...

    My question is: which is the best? The clocked process approach? Or
    non-clocked t and Y-assignments?

    Can you clarify a little for me?

    Thanks a lot,

    -Walala
     
    walala, Sep 9, 2003
    #3
  4. It sounds like your entire design is combinatorial from input 'X' to
    output 'Y'. Is that right? If so, please ignore my comment about
    flip flops.

    ....
    Yet another way of avoiding large sensitivity lists is to use
    concurrent statements instead of processes. Look up the syntax for a
    concurrent assignment statement in a text book for ideas.

    Regards,
    Allan.
     
    Allan Herriman, Sep 9, 2003
    #4
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