walala said:
Dear all,
I want to ask a question about FILE I/O using VHDL during
simulation. My project requires a close collaboration between matlab
and VHDL simulation. I need to import data generated from matlab
into VHDL program and then execute and get results exported into
matlab for further analysis.
Is there a way to open/save file for exchanging data in VHDL?
VHDL has reasonable file I/O facilities, described in any
good textbook (try Peter Ashenden, Designer's Guide to VHDL).
Standard file I/O will work fine if you can run your MATLAB
program, generate a file of data and then read that file into
your VHDL simulation; similarly you can get VHDL to dump some
output to a file and then post-process with MATLAB.
If you need on-the-fly interaction between MATLAB and VHDL,
things are more difficult. There is no easy way to open
a pipe from VHDL. However, we've had quite good success
by using Tcl to glue a VHDL simulation to another running
program. Use VHDL's console I/O (INPUT and OUTPUT channels),
and then use Tcl to open the simulator as a bidirectional
command pipeline. Similarly Tcl can then open a MATLAB
program as a bidi command pipe. You can then manage the
interaction between simulation and MATLAB, using Tcl.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services
Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
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