are there FILE I/O in VHDL?

W

walala

Dear all,

I want to ask a question about FILE I/O using VHDL during
simulation. My project requires a close collaboration between matlab
and VHDL simulation. I need to import data generated from matlab
into VHDL program and then execute and get results exported into
matlab for further analysis.

Is there a way to open/save file for exchanging data in VHDL?

Thanks a lot,

-Walala
 
E

Egbert Molenkamp

Yes,
It is possible to read and write files within VHDL.
See for more informatie the FAQ:
http://www.vhdl.org/vi/comp.lang.vhdl/FAQ1.html#files

Depending on your simulator it is probably possible to
start the VHDL simulation from the MatLab environment.
We use this apporach in combination with ModelSim.
Here an example how we used it for a fft implementaion.

A part of the matlab script is:
%--> Start ModelSim and start simulation
dos('M:\win32\vsim -do V:/testbench/fft1024/fft1024.do');

where de script file "fft1024.do" contains the ModelSim commands.
e.g.:
cd W:/
vcom V:/testbench/fft1024/fft1024_tester.vhd
vcom V:/testbench/tp_testbench.vhd
vsim tp_testbench
run -all
quit -f

Using this approach we automatically can compare the VHDL simulation
results (results are written in a file in ModelSim) with the MatLab results.

Egbert Molenkamp
 
J

Jonathan Bromley

walala said:
Dear all,

I want to ask a question about FILE I/O using VHDL during
simulation. My project requires a close collaboration between matlab
and VHDL simulation. I need to import data generated from matlab
into VHDL program and then execute and get results exported into
matlab for further analysis.

Is there a way to open/save file for exchanging data in VHDL?

VHDL has reasonable file I/O facilities, described in any
good textbook (try Peter Ashenden, Designer's Guide to VHDL).

Standard file I/O will work fine if you can run your MATLAB
program, generate a file of data and then read that file into
your VHDL simulation; similarly you can get VHDL to dump some
output to a file and then post-process with MATLAB.

If you need on-the-fly interaction between MATLAB and VHDL,
things are more difficult. There is no easy way to open
a pipe from VHDL. However, we've had quite good success
by using Tcl to glue a VHDL simulation to another running
program. Use VHDL's console I/O (INPUT and OUTPUT channels),
and then use Tcl to open the simulator as a bidirectional
command pipeline. Similarly Tcl can then open a MATLAB
program as a bidi command pipe. You can then manage the
interaction between simulation and MATLAB, using Tcl.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: (e-mail address removed)
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
H

Hans

Hi Walala,

Instead of files you might also want to have a look at using sockets.
Sockets are surprisingly easy to use especially under Linux :)

If you have access to Modelsim PE you can use TCL to support sockets. If you
have Modelsim SE you can also use the excellent FLI (C/C++) interface.


Hans

www.ht-lab.com
 
A

Arvind Kumar

Hi,
Any pointer to how the socket which you mentioned and what can it do???
Regards,
Arvind Kumar
 

Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments. After that, you can post your question and our members will help you out.

Ask a Question

Members online

Forum statistics

Threads
473,744
Messages
2,569,482
Members
44,901
Latest member
Noble71S45

Latest Threads

Top