ASIC RTL and FPGA RTL


A

Anand P Paralkar

Hi,

I was talking to an "expert" in synthesis and he mentioned that there is
a lot of difference between a synthesizable RTL code for a FPGA and a
synthesizable RTL code for an ASIC.

Is this true?

If so, could you please point the significant differences between the
two and what causes these differences.

Thanks,
Anand
 
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Helo
Can anybody please guide me the relation between embedded RAM blocks and CLB Slices of Virtex 7 FPGA????
I want to compare the area in the form of CLB Slices and i am using 30 Embedded RAM Blocks of Virtex 7 FPGA.
 

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