ASIC RTL and FPGA RTL

Discussion in 'VHDL' started by Anand P Paralkar, Apr 26, 2004.

  1. Hi,

    I was talking to an "expert" in synthesis and he mentioned that there is
    a lot of difference between a synthesizable RTL code for a FPGA and a
    synthesizable RTL code for an ASIC.

    Is this true?

    If so, could you please point the significant differences between the
    two and what causes these differences.

    Thanks,
    Anand
     
    Anand P Paralkar, Apr 26, 2004
    #1
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  2. Alexander Gnusin, Apr 26, 2004
    #2
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  3. Anand P Paralkar

    Yasir Khizar

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    Helo
    Can anybody please guide me the relation between embedded RAM blocks and CLB Slices of Virtex 7 FPGA????
    I want to compare the area in the form of CLB Slices and i am using 30 Embedded RAM Blocks of Virtex 7 FPGA.
     
    Yasir Khizar, Nov 7, 2016
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