assigning output to input

Discussion in 'VHDL' started by Simone Winkler, Aug 28, 2003.

  1. Hello!

    I tried to do a RS-flip-flop with nor-gates in VHDL. But i got the following
    error message:

    Parameter notq of mode out can not be associated with a f
    ormal parameter of mode in.

    the vhdl code was:

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;

    entity rs is
    Port ( S : in std_logic;
    R : in std_logic;
    Q : out std_logic;
    notQ : out std_logic);
    end rs;

    architecture Behavioral of rs is

    Q <= S nor notQ;
    notQ <= R nor Q;
    end Behavioral; was just to try the functionality of vhdl......
    what can i do to solve this problem?

    Simone Winkler, Aug 28, 2003
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  2. Sounds like you may have two problems.

    First, your code is trying to use the value of an "out" port,
    which is illegal in VHDL. You must create an internal signal, use
    that internal signal for all the useful work, and then copy it
    to the out port(s).

    Second, the error message: it sounds as if your testbench for
    this module is connecting to the ports inappropriately - or
    perhaps it's just a confusing error message.
    You don't need arithmetic packages for this code.
    Get rid of them.
    OK so far.
    architecture Corrected of rs is
    signal Q_int: std_logic;
    signal Qbar_int: std_logic;
    Q_int <= S nor Qbar_int; -- this is OK
    Qbar_int <= R nor Q_int;
    -- now get the signals out to the ports:
    Q <= Q_int;
    notQ <= Qbar_int;
    end Corrected;
    OK, but be aware that combinational feedback is always a bad
    idea for synthesisable logic.

    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
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    Jonathan Bromley, Aug 28, 2003
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