asychronous sram read and write

[yali]

Hi

I use a CPU's SRAM interface to write data to the dual port RAM in Xilinx
FPGA, CPU only output PCI bus clock to FPGA, not system clock.

it seems the write is not succesful because of asychronous clock issue,is
there any good suggestion?Thanks

yali

 

[Javier Castillo]

Hello:

I don´t know what is exactly the problem but if you are working in a FPGA
you can take the system clock from its input pin and take them to the SRAM
interface.

Regards
Javier Castillo
(e-mail address removed)
www.opensocdesign.com

 

[anupam]

Hi yali,
It seems that CPU is giving the only address bus and data bus 2 FPGA .
Here I suggest 2 use a saperate clock for FPGA writing and at least one
rising edge should be available during write or read cycle.
Then Read n Write to FPGA will be successful.
Regards
Anupam