asychronous sram read and write

Discussion in 'VHDL' started by yali, Aug 28, 2004.

  1. yali

    yali Guest

    Hi

    I use a CPU's SRAM interface to write data to the dual port RAM in Xilinx
    FPGA, CPU only output PCI bus clock to FPGA, not system clock.

    it seems the write is not succesful because of asychronous clock issue,is
    there any good suggestion?Thanks

    yali
     
    yali, Aug 28, 2004
    #1
    1. Advertisements

  2. Hello:

    I donĀ“t know what is exactly the problem but if you are working in a FPGA
    you can take the system clock from its input pin and take them to the SRAM
    interface.

    Regards
    Javier Castillo

    www.opensocdesign.com
     
    Javier Castillo, Aug 30, 2004
    #2
    1. Advertisements

  3. yali

    anupam Guest

    Hi yali,
    It seems that CPU is giving the only address bus and data bus 2 FPGA .
    Here I suggest 2 use a saperate clock for FPGA writing and at least one
    rising edge should be available during write or read cycle.
    Then Read n Write to FPGA will be successful.
    Regards
    Anupam
     
    anupam, Aug 31, 2004
    #3
    1. Advertisements

Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.