Asynchronous up/down counter

[Jan Behrend]

Hello list,

the CY7C460A is an 8k deep, asynchronous FIFO :

ftp://ftp.mpifr-bonn.mpg.de:/outgoing/jbehrend/cy7c460a.pdf

What I want to do is to precisely keep track of the fill level. So I
need a counter which reacts to falling edges of two asynchronous signals
(/WR /RD).
This design is to be put into a Xilnix Coolrunner CPLD (Xpla3).

Has anyone done this before or can help how to go about this?

Cheers Jan Behrend

--
Jan Behrend
Max-Planck-Institut für Radioastronomie
Abteilung für Infrarot-Interferometrie Tel: (+49) 228 525 319
Auf dem Hügel 69 Fax: (+49) 228 525 411
D-53121 Bonn (Germany) (e-mail address removed)
http://www.mpifr-bonn.mpg.de
PGP public key:
ftp://ftp.mpifr-bonn.mpg.de:/outgoing/jbehrend/jbehrend-gpg.asc

 

[Dave Pollum]

Hello list,

the CY7C460A is an 8k deep, asynchronous FIFO :

ftp://ftp.mpifr-bonn.mpg.de:/outgoing/jbehrend/cy7c460a.pdf

What I want to do is to precisely keep track of the fill level. So I
need a counter which reacts to falling edges of two asynchronous signals
(/WR /RD).
This design is to be put into a Xilnix Coolrunner CPLD (Xpla3).

Has anyone done this before or can help how to go about this?

Cheers Jan Behrend

--
Jan Behrend
Max-Planck-Institut für Radioastronomie
Abteilung für Infrarot-Interferometrie Tel: (+49) 228 525 319
Auf dem Hügel 69 Fax: (+49) 228 525 411
D-53121 Bonn (Germany) (e-mail address removed)
http://www.mpifr-bonn.mpg.de
PGP public key:
ftp://ftp.mpifr-bonn.mpg.de:/outgoing/jbehrend/jbehrend-gpg.asc

I've worked with a smaller async FIFO (Cypress CY7C425), and have found
the Full and Empty flags to be adequate for my needs. By counting the
/WR and /RD signals aren't you duplicating some of the FIFO's internal
logic? Perhaps doing the whole thing in an FPGA would fit your needs
better. I haven't graduated out of CPLDs yet, so I can't help you, but
there have been discussions of doing FIFOs in FPGAs in comp.arch.fpga
or comp.lang.vhdl.

-Dave Pollum

 

[Jan Behrend]

I've worked with a smaller async FIFO (Cypress CY7C425), and have found
the Full and Empty flags to be adequate for my needs. By counting the
/WR and /RD signals aren't you duplicating some of the FIFO's internal
logic?

This is certainly true, so somebody HAS done it.
I need the exact fill level because I am sending packets over an
IEEE-1394 bus, and I want to adjust the packet size according to the
amount of available data. Another requirement is to completely empty
the FIFO once no more new data arrive. That's why the fill flags are to
coarse for my needs.

Perhaps doing the whole thing in an FPGA would fit your needs
better.

The hardware choice is already fixed.

I haven't graduated out of CPLDs yet, so I can't help you, but
there have been discussions of doing FIFOs in FPGAs in comp.arch.fpga
or comp.lang.vhdl.

Thanks for the pointer.

-Dave Pollum

--
Jan Behrend
Max-Planck-Institut für Radioastronomie
Abteilung für Infrarot-Interferometrie Tel: (+49) 228 525 319
Auf dem Hügel 69 Fax: (+49) 228 525 411
D-53121 Bonn (Germany) (e-mail address removed)
http://www.mpifr-bonn.mpg.de
PGP public key:
ftp://ftp.mpifr-bonn.mpg.de:/outgoing/jbehrend/jbehrend-gpg.asc