Bad synchronous description, but why ?

Discussion in 'VHDL' started by Roman Himmes, Jun 21, 2005.

  1. Roman Himmes

    Roman Himmes Guest


    I am very new to VHDL and I still haven't figured everything out.
    In this code I get: "Signal tmprr cannot be synthesized, bad synchronous
    description" I understand that this is due to possible that more than one
    process is accessing Signals ...

    My Process in which I have the Problem is this code:

    RR_PROCESS: process(RR,Send,maxDelay)
    variable tmprr : std_logic_vector(11 downto 0) := "000000000000";
    if RR='1' and RR'event then tmprr := tmprr + 1;
    if Send='1' then
    case maxDelay is
    when "00" => tmprr := To_StdLogicVector( To_BitVector(tmprr) sla 1);
    when "01" => tmprr := To_StdLogicVector( To_BitVector(tmprr) sla
    when others => tmprr := To_StdLogicVector( To_BitVector(tmprr) sla
    end case;
    sRRight <= EXT(tmprr,8);
    tmprr := "000000000000";
    end if;
    end if;
    end process;

    Other relevant signals:
    signal maxDelay : std_logic_vector (1 downto 0) := "00";
    signal Send : std_logic := '0';
    and Ports:
    RR : in std_logic;
    sRRight : out std_logic_vector(7 downto 0));

    Where is the problem ? I cannot see it !

    Thanx for any comment

    Roman Himmes
    Roman Himmes, Jun 21, 2005
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  2. Synthesis is expecting:

    RR_PROCESS: process(clock, reset) or

    RR_PROCESS: process(clock)

    Anything else is a "bad synchronous description"
    Have a look at some code examples.

    -- Mike Treseler
    Mike Treseler, Jun 21, 2005
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  3. Roman Himmes

    Roman Himmes Guest

    So every process has to be be synchronized with the clock signal ?
    So if you want to make a process sensible to another signal you have to do
    something like

    process(clock, signal_var)
    if clock = '1' and clock'event then
    if signal_var='1' then
    -- do stuff
    end if;
    end if;
    end process;

    -- Roman Himmes
    Roman Himmes, Jun 21, 2005
  4. Roman Himmes

    Klaus Falser Guest

    I'm really wondering why every VHDL beginner is using
    the "if clock = '1' and clock'event" phrase
    insteadt of the "rising_edge()" function.

    Are all the books around that old or the teachers that oldfashioned?
    Please, please, VHDL beginners all over the world, start writing

    if rising_edge(clock) then
    end if;

    Roman, to answer you question:
    If you have to write VHDL code which has to be synthesized and put
    into a FPGA or CPLD, then nearly all the processes are synchronous to
    one or more clock signals.
    This comes from the fact that the core elements of digital logic
    are flip-flops, and flip-flops are active only at the rising or
    falling edge of a clock signal.

    In your example the "do stuff" is done synchronous to the
    clock signal, but only at the rising edges where signal_var = '1'.
    Signal_var acts as a "clock enable" signal.

    Your process needs NOT to be sensitive to signal_var.
    Just to explain :
    A process is waiting that one or more signal mentioned in the
    sensitivity list changes. After that the body of the process
    is executed and the waiting starts again.
    Making your process sensitive to signal_var will not change
    anything, since the do_stuff statements are only reached when
    clock'event is true and clock'event is only true when the clock
    signal changes.

    Hope this helps, but probabely it's best if you read
    some book about digital logic too.

    Klaus Falser
    Klaus Falser, Jun 21, 2005
  5. Roman Himmes wrote:

    Do not use else / elsif after an 'event in a preceding if-clause. What
    do you expect that this could be in real world?

    Note: There is only one exception from this rule: Some (but very few)
    synthesis tools support dual-edge flipflops and they are coded using two
    succeeding if-clauses containing an 'event. But in general: Don't do this.

    Use the template for flipflops:

    process(reset, clock)
    if (reset='1') then
    -- do some asynchronous reset
    elsif rising_edge(clock) then
    -- do some synchronous stuff
    end if;
    end process;

    Ralf Hildebrandt, Jun 21, 2005
  6. Roman Himmes

    Andy Peters Guest

    You should start by reading the documentation that comes with your
    synthesis tool. I've used four or five different synthesis tools, and
    the docs for each have a section usually titled something like "The Art
    Of VHDL Synthesis."

    Read it. Your questions will be answered.

    Andy Peters, Jun 21, 2005
  7. Roman Himmes

    Andy Peters Guest

    Worse -- the docs that come with the synthesis tools haven't been
    updated since the days of VHDL '87. That's why you still see examples
    that use std_logic_arith instead of numeric_std.

    Andy Peters, Jun 21, 2005
  8. Roman Himmes

    Bert Cuzeau Guest

    Sorry, this is wrong also !
    Sensitivity list in this case must be process(clock) _only_.
    Neither Clock Enable nor anything else than an async action
    should be in such (sequential) sensitivity list.
    And as other pointed out, rising_edge is indeed looking better.

    Coding in VHDL wihtout basic know-how is, imo, hopeless...

    Bert Cuzeau
    Bert Cuzeau, Jun 22, 2005
  9. Roman Himmes

    Duane Clark Guest

    While strictly true, it won't make a difference either in simulation or
    synthesis. The "clock'event" (which is also implied when using
    rising_edge) means that the contained logic will only be executed at the
    proper time; a change in signal_var will not cause a clock event. But of
    course the code should be written properly.
    Duane Clark, Jun 22, 2005
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