Hi,
I have an example:
In my VHDL code I have two unsigned signals
signal sDataR : unsigned (9 downto 0);
signal sR : unsigned (1 downto 0);
I want to add bit 1 of sR to sDataR. sDataR + sR(1) doesn't work. I will
get the following error:
ERROR: cannot convert type std_ulogic to type unsigned
How can I add one bit of an unsigned signal to another unsigned signal?
Thank you for your answer.
bye
martin sauer
Definatly use numeric_std, because it is an actual IEEE standard,
std_logic_unsigned is not - it was origionally defined by Synopsys and
compiled (wrongly) in to the IEEE library. Different vendors implement
std_logic_unsigned differently, whereas the IEEE defined numeric_std.
As for your error, sR(1) is just a single bit, which is why you're
getting the problem. Addition has to be done on 2 unsigned numbers
that have the same length that match the result length. So, the best
way around your problem:
signal output : unsigned(10 downto 0); --addition output will be 1
bit bigger than largest input if you dont want overflow
...
output <= ('0' & sDataR) + resize(sR, output'length);
--'0' is concatenated the make sDataR 11 bits.
if you really wanted to add a single bit from sR then you have to use
a range to keep it as an unsigned type. Indexing just 1 returns a
std_ulogic, as you found.:
output <= ('0' & sDataR) + resize(sR(1 downto 1), output'length);
