Hey there ... I got this VHDL problem as an exam question and it kinda freaked me out .. had no idea where to even begin and hence, got like 2 marks out of 20.\r\n\r\nI do want to know how to program these though:\r\n\r\nHere are the questions:\r\n\r\n[IMG]http://i91.photobucket.com/albums/k320/shahilj/q31.jpg[/IMG]\r\n[IMG]http://i91.photobucket.com/albums/k320/shahilj/q32.jpg[/IMG]\r\n\r\nMy attempt at Q1 (which I think is wrong)\r\n\r\nEntity Bus is\r\nBegin\r\n port(write1, write2, write3: in std_logic;\r\n wdata1, wdata2, wdata3: in bit_vector(7 downto 0);\r\n f: out bit_vector(7 downto 0));\r\n-\- The f variable is what I think is wrong.\r\nEnd Bus;\r\n\r\nArchitecture Behaviour of Bus is\r\nBegin\r\n f <= wdata1 when write1 = "1" else\r\n wdata2 when write2 = "1" else\r\n wdata3 when write3 = "1";\r\nEnd Behaviour;\r\n\r\n-\-\r\n\r\nFor Q2 .. I was VERY unsure ... What I did was treat the entire structure as the Entity with the inputs:\r\nio_port_data, address_rf, write_rf\r\nI'm not sure if the control signals (load_accumulator, bus_rf, bus_alu, bus_ioport) are to be declared in the Entity. \r\n\r\nWhat confused me is that this Bus has output ports, unlike the Entity described above. Also, I don't know how to program the the registers. This question made up 20 percent of the exam .. If I did get 20/20 .. I would have passed :( PLEASE help!!