Changing generics in top-level module

[Martin Thompson]

Hi all,

Is there a way of changing the generics of the top-level entity from a
configuration?

My testbench has some parameters I'd like to tweak on different runs,
and I would like to do it via multiple configurations, rather than
vsim options. However, I can't figure out how to do it!

My current solution involves instantiating this top level testbench in
an even higher level entity, which I can then use configurations on,
but this seems wasteful...

Any suggestions greatly appreciated!

Thanks,
Martin

 

[Egbert Molenkamp]

Not yet, there is a proposal on this, see
http://www.eda.org/vhdl-200x/vhdl-200x-ft/proposals/proposals.html (FT23)
Egbert Molenkamp

 

[Alan Fitch]

Hi all,

Is there a way of changing the generics of the top-level entity from a
configuration?

My testbench has some parameters I'd like to tweak on different runs,
and I would like to do it via multiple configurations, rather than
vsim options. However, I can't figure out how to do it!

My current solution involves instantiating this top level testbench in
an even higher level entity, which I can then use configurations on,
but this seems wasteful...

Any suggestions greatly appreciated!

As Egbert says, not yet. In the current VHDL LRM it says that a
particular
implementation of the language is not required to support ports and
generics
on a top level entity, though it may.

Using a wrapper (or donut as the Americans say) is one approach, as
you've
taken.

You can sometimes use simulator features, for instance vsim -g in
modelsim.
You could then write a set of scripts to launch simulation runs with
different
top level generics. Of course this isn't as portable as using a
wrapper.

regards

Alan


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[Martin Thompson]

Thanks for those inputs - looks like a wrapper for now then.

Cheers,
Martin

 

[Jim Lewis]

The latest is that this proposal has been demoted
to the MP list. I will be updating the reflector
to indicate this shortly.

How much we get done and how fast we can do it
is really a function of participation. Hint. Hint.
Hint. Observer participants (no membership required)
with a good knowledge of the VHDL LRM are welcome
to write an LCS (Language Change Specification).

Things get worked on based on priority and based on
someone being willing and having the time to write
an LCS. This item rolled off the fast track list
due to priority, required delivery schedule for
fast track items (must have an LCS by DAC), and
not enough bandwidth from the current members (we
tend to take time off to sleep, say hi to the wife,
and play with the kids). It is a volunteer effort,
so for most it means our job does not pay us to do
the work.

Cheers,
Jim
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1-503-590-4787

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[Just an Illusion]

Hi Martin,

I know that configuration isn't supported for RTL synthesis
(IEEE-1076.6-1999), but have you try to change your generics via the
configuration binding ?

I remember you that in IEEE-1076-2002, chapter 5.2, the configuration
specification can include some aspect of generic_map_aspect (see section
2.5.1).

I don't know how simulator implement it, but that can be your solution.

JaI