composite inout signals with different driver directions

  • Thread starter Ralph Friedrich
  • Start date

R

Ralph Friedrich

Hello,
I'm use vectors to combine signals with different driver directions.
May be that's not a good coding style ?!


T(
Q : INOUT Std_logic_vector (24 DOWNTO 0) ;
....

For example:
Q(12 downto 0) is driven by the testbech.
Q(24 downto 13) is driven by DUT.

In the simulation I get there a X on some signals.

When I set a init value to the vector it works sometimes.

Does anyone know whats going on?
 
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J

Jim Lewis

Ralph,
Initially the testbench and the DUT are driving
driving all elements of the array. If one does
not drive a field, the value it is effectively
driving is 'U', the left most value of std_ulogic.

A simple way to get around this is to initialize
the port to all 'Z' as follows:

T(
Q : INOUT Std_logic_vector (24 DOWNTO 0) := (others => 'Z') ;
...

Cheers,
Jim

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Jim Lewis
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