composite inout signals with different driver directions

Discussion in 'VHDL' started by Ralph Friedrich, Nov 7, 2003.

  1. Hello,
    I'm use vectors to combine signals with different driver directions.
    May be that's not a good coding style ?!

    Q : INOUT Std_logic_vector (24 DOWNTO 0) ;

    For example:
    Q(12 downto 0) is driven by the testbech.
    Q(24 downto 13) is driven by DUT.

    In the simulation I get there a X on some signals.

    When I set a init value to the vector it works sometimes.

    Does anyone know whats going on?
    Ralph Friedrich, Nov 7, 2003
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  2. Ralph Friedrich

    Jim Lewis Guest

    Initially the testbench and the DUT are driving
    driving all elements of the array. If one does
    not drive a field, the value it is effectively
    driving is 'U', the left most value of std_ulogic.

    A simple way to get around this is to initialize
    the port to all 'Z' as follows:

    Q : INOUT Std_logic_vector (24 DOWNTO 0) := (others => 'Z') ;


    Jim Lewis
    Director of Training mailto:
    SynthWorks Design Inc.

    Expert VHDL Training for Hardware Design and Verification
    Jim Lewis, Nov 7, 2003
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