Hi all\n\nI've just started to learn VHDL having previously coded a bit in\nVerilog. I'm aiming to write synthesisable VHDL code at RTL. I'm\nhaving trouble getting my head around concurrent signal assignments.\n[QUOTE]\nFrom what I've read about VHDL, concurrent seems to be a bad[/QUOTE]\ndescription. One might be tempted to interpret the concurrent\nassignment:\n\na<=b\nc<=a\n\nAs at the same time a gets assigned the value of b, and c gets assigned\nthe OLD value of a. Would a better way of describing concurrent\nassignment be "the order of assignment doesn't matter" - this is\nbecause of the event processing/process execution cycles, right?\n\nI'm pretty sure that concurrent assignment from a synthesisable VHDL\npoint of view just represents how signals will be 'wired'.\n\na<=b\nc<=a\n\njust describes the fact that b is wired to a, and a is wired to c:\n\n-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-b-\-\-\-\-\-\-\-\-\-\-\-\n|\na\n|\n-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-c-\-\-\-\-\-\-\-\-\-\-\-\n\nsomething like:\n\na<= b or c\nd <= a and c\n\nwould represent something like\n\n-\-\-\-\-b-\-\-\-\-\-\-\-\-\-|-\-\-|\n|OR |-\-\-\-\-a-\-\-\-\-|-\-\-\-|\n-\-\-\-\-c-\-\-\-\-\-\-\-\-\-|-\-\-| |AND |\n| | |-\-\-\-\-\-\-\-d-\-\-\-\-\-\-\-\n-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-\-|-\-\-\-|\n\nDoes this stuff sound right?\n\nThanks in advance\n\nTaras\n\nPS: I realise I posted not too long before this message. I decided to\nput it all into one message would be too big.