constant integer to unsigned casting

Discussion in 'VHDL' started by Limor, Mar 22, 2011.

  1. Limor

    Limor

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    Hi
    I'm running a benchmark between Modelsim and active HDL.
    I have the following code compiled on Active HDL:

    addr := unsigned(x"1");

    When I run it on Modelsim, it requires a ' sign after the unsigned , in order to compile. So in Modelsim it looks like this:

    addr := unsigned'(x"1");

    This expression also compiles on Active HDL.

    Can any body explain why do I need this ' sign?

    Thanks
    Limor
     
    Limor, Mar 22, 2011
    #1
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