conversions

Discussion in 'VHDL' started by Max, Sep 11, 2003.

  1. Max

    Max Guest

    I use xilinx ise webpack 5.2

    how can I converte datas?
    for example integer to std_ulogic_vector, or std_logic_vector to
    unsigned.

    I need a function list as wide as possible.
    please tell me which package I need to use (IEEE.STD_LOGIC_UNSIGNED is
    not standardized, isn't it?)

    thanks
     
    Max, Sep 11, 2003
    #1
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