Discussion in 'VHDL' started by Max, Sep 9, 2003.

  1. Max

    Max Guest

    I write the following decoder:

    ce <= "0001" when addr = "0--" else
    "0010" when addr = "10-" else
    "0100" when addr = "110" else

    it doesn't work.

    Then I tried this one:

    ce <= "0001" when addr(2) = '0' else
    "0010" when addr(2 downto 1) = "10" else
    "0100" when addr = "110" else

    this work.

    why the first version doesn't work?
    the symbol '-' means "don't care", isn't it? So why it is wrong?
    I prefer something like the first version since is less cryptic.

    Max, Sep 9, 2003
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  2. I am interested by this issue. Which compiler are you using?

    Laurent Gauch
    Amontec Team, Laurent Gauch, Sep 9, 2003
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  3. In the package std_logic_1164 the type std_(u)logic is declared.
    For this type implicitly an overloaded function for "=" is declared. This
    function is straightforward. In case left and right is exactly te same the
    result is true.
    And I think you did not expect this behavior?

    Now for type std_logic the interpretation of '-' is dont care.
    This omission is repaired in the package NUMERIC_STD with the std_match
    The next example will have the expected behavior (I hope).

    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;
    USE ieee.numeric_std.ALL;
    ENTITY decoder IS
    PORT (addr : std_logic_vector(2 DOWNTO 0);
    ce : OUT std_logic_vector(3 DOWNTO 0));
    END decoder;

    ARCHITECTURE beh OF decoder IS
    ce <= "0001" when std_match(addr, "0--") else
    "0010" when std_match(addr, "10-") else
    "0100" when std_match(addr, "110") else
    END beh;

    Sometimes (often) you see the use of the package std_logic_unsigned or
    std_logic_signed. These packages include also an overloaded function "=" for
    std_logic_vector. However if you write:
    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;
    USE ieee.std_logic_unsigned.ALL; -- not an ieee package!
    Then there are two overloaded function for "="; the one implicitly defined
    in std_logic_1164 and the explict one in std_logic_unsigned.
    A VHDL compliant tool should complain .. but some tools support it (the
    explicit declaration is used). Sometimes there is a compiler option
    ("explicit declaration").

    If the decoder is large you could also try another apporach. Although the
    behaviour is not the same it may give you some ideas:

    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;
    ENTITY bin2dec IS
    GENERIC (width : natural := 3);
    PORT (a : IN std_logic_vector( width-1 DOWNTO 0);
    b : OUT std_logic_vector ( 2**width-1 DOWNTO 0));
    END bin2dec;

    LIBRARY ieee;
    USE ieee.numeric_std.ALL;
    ARCHITECTURE demo OF bin2dec IS
    PROCESS (a)
    END demo;

    Egbert Molenkamp
    Egbert Molenkamp, Sep 9, 2003
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