delay using integrator

[Sarah]

I want to use the output of a R-C integrator as a delayed input to CPLD

(inside there is a XOR gate and counter logic). It worked OK when I use

discrete XOR IC 4070. But for same R-C values it doesn't works with
CPLD.
Is is due to the fact that analog input (sawtooth from integrator) has
given to CPLD?
Is comparator after integrator is one of the solution?
Suggest other methods for creating delays inside CPLD. That will
elliminate need of integrator. Here delay required is 1.1us.

 

[jens]

Use a clock and a counter. Then the accuracy of the delay is based on
clock accuracy and not analog component tolerances.

 

[Ashu]

Hi,
Firstly whatever your design is you need to make you want it to go high
and detected by logic when it increases above voltage say 'v' else it
will go high when it reaches VIH of the IC(cpld or Xorr IC whichever u
use).
If these two devices are using diff technologies their VIH values will
differ.

If this is not a problem then to create a delay u can use a multiple
flipflop stages and provide them appropriate clock.
A simple shift register will also do.