determine slv width by given integer range

[Olaf]

Hi,

maybe I did not seek the c.l.vhdl FAQ very carefully, but I did not
found a way to determine the bit width of a std_logic_vector/unsigned by
a given integer range. What I want to do is like this:

subtype level_t is integer range 0 to 8; -- width 3 downto 0
signal level : unsigned(?? downto ??); -- can hold level_t range

Is there a way?

Thanks
Olaf

 

[Nicolas Matringe]

Olaf a écrit :

Hi,

maybe I did not seek the c.l.vhdl FAQ very carefully, but I did not
found a way to determine the bit width of a std_logic_vector/unsigned by
a given integer range. What I want to do is like this:

subtype level_t is integer range 0 to 8; -- width 3 downto 0
signal level : unsigned(?? downto ??); -- can hold level_t range

Is there a way?

You need a log2 function (search for it, there are a few available) :

signal level : unsigned(log2(level_t'high) downto 0);

Nicolas

 

[Paul Uiterlinden]

You need a log2 function (search for it, there are a few available) :

signal level : unsigned(log2(level_t'high) downto 0);

See http://www.vhdl.org/comp.lang.vhdl/FAQ1.html#4.10

 

[Mike Treseler]

maybe I did not seek the c.l.vhdl FAQ very carefully, but I did not
found a way to determine the bit width of a std_logic_vector/unsigned by
a given integer range. What I want to do is like this:

see int2sgn source here:
http://home.comcast.net/~mike_treseler/
for some related functions.

-- Mike Treseler