Different concatenation result VJDL93' generates from VHDL'87

Discussion in 'VHDL' started by bigdipper_gary, Jan 2, 2004.

  1. Hello there!

    I hope i could get some help regarding concatenation.
    Part of my VHDL code of a Booth Multiplier is appended below. This code tries to generate Partial Product term in a Booth Multiplier. The inputs x and y are generic and the output which is given as matrix is a two dimentional array data output.
    procedure gen_pp_Booth ( x : in std_logic_vector
    (n-1 downto 0);
    y: std_logic_vector (m-1 downto 0);
    PP: inout matrix) is

    variable i,j,k : integer;
    variable nb_pp : integer;
    variable x_coded : std_logic_vector (n+1 downto 0);
    variable selector : std_logic_vector (2 downto 0);


    for i on 0 to (n-1) loop
    x_coded (i+1) := x(i);
    end loop;
    x_coded (0):= '0';
    nb_pp := n/2;

    j:= 0; -- index for the selector

    for i in 0 to (nb_pp -1) loop
    selector := x_coded(j+2) & x_coded(j+1) & x_coded(j);
    -- ( this is where the warning is)
    case selector is

    when "000" =>
    for k in 0 to (m+n-1) loop
    PP(i)(k) := '0';
    end loop;

    when "001" =>
    when "010" =>
    when others => null;
    end case;
    j := j+2;
    end loop;
    end procedure gen_PP_Booth;

    When this code is simulated using NC Sim ( Cadence) , there was no error however when the Booth Multiplier was used in synthesis using Design analzer of Synopsys, a warning was generated while in elebrotation phase. The warning is that " the VHDL'93 concatenation operator generates different results from the same operator in VHDL'87".
    The warning is on the concatination operation for the selector of the VHDL code given above.

    My question is that basing on the code given above, would my selector generate different logic circuits in VHDL'93?
    Is my code written using VHDL'87?
    How could I then rephrase it to suit the VHDL'93 style of coding for the cocatenation for the selector?
    I have used VHDL'93 during my simulation by default and in design analyzer , I think VHDL'93 coding style is automatically reffered to for synthesis

    I would appreciate if I could get some response to my problem.
    Thanks in advace.


    bigdipper_gary, Jan 2, 2004
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  2. After fixing the syntax error:

    for i in 0 to (n-1) loop
    -- for i on 0 to (n-1) loop

    and assuming a reasonable type for "matrix",
    your procedure compiles fine for -87 or -93 using modelsim.

    -- Mike Treseler
    Mike Treseler, Jan 5, 2004
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