Does anyone have the I2C vhdl code and work for Altera Flex10K FPGA?

Discussion in 'VHDL' started by underground, Jul 19, 2004.

  1. underground

    underground Guest

    When I code a simple I2C interface using VHDL,I suffer a critical problem
    that is about synthesizing the tri-state
    buffer(inout) because of sending the "Ack" to the master interface from
    the designed slave when the mode at "slave receiver".
    Firstly I thought that might be the problem about compiler
    sofeware(MaxplusII) because the I found that many people said the
    "MaxplusII" couldn't synthesize the "tri-state" case because of the
    "LCell"(possibily..) or something...
    So I tried to compiled my code using "QuartusII" and then simulated it,but
    the simulation result still didn't happen and I thought my problem might
    be caused by either "The code wrong.." or "the FPGA(FLEX10K30RC240-3)
    can't realize
    the tri-state.."(Some people also said that in the web.)
    But when I mailed to the Altera Corp.,the engineer told me
    that the tri-state in FLEX10K could be realized...
    So,I want to find someone here to do me a favor.
    If the tri-state can be realized in FLEX10K,how do I modify
    my code?
    Does anyone(worked for this before) can provide me your code
    or suggestions? I will appreciate very much.

    underground
     
    underground, Jul 19, 2004
    #1
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  2. Re: Does anyone have the I2C vhdl code and work for Altera Flex10KFPGA?

    underground wrote:
    > When I code a simple I2C interface using VHDL,I suffer a critical problem
    > that is about synthesizing the tri-state
    > buffer(inout) because of sending the "Ack" to the master interface from
    > the designed slave when the mode at "slave receiver".


    Post your code :eek:)
    Hi-Z and I²C work in Altera Flex

    Nicolas
     
    Nicolas Matringe, Jul 19, 2004
    #2
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  3. underground

    underground Guest

    Re: Does anyone have the I2C vhdl code and work for Altera Flex1

    My code was described below..
    I have already confused with my code,so if you can modify it then I will
    appreciate you very much....
    But how do I post my waveform(has already been saved in JPG)
    with my reply in this web? or Do you mind to give me you email address?
    underground
    ___________________________________________________________

    LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    USE ieee.std_logic_arith.all;
    USE ieee.std_logic_unsigned.all;

    ENTITY i2c_integration IS
    PORT (
    SDA : INOUT std_logic;
    SCL : IN std_logic;
    RST : IN std_logic;
    READOUT : OUT std_logic;
    D_OUT : OUT std_logic_vector(4 DOWNTO 0);
    StartOrStop_OUT : OUT std_logic;
    INTERRUPT_OUT : OUT std_logic
    );
    END i2c_integration;

    ARCHITECTURE i2c OF i2c_integration IS


    TYPE state IS (IdleState, AddressState, AckState, DataState);
    SIGNAL Present_State : state;
    SIGNAL Next_State : state;
    SIGNAL D_BUFFER : std_logic_vector(7 DOWNTO 0);
    SIGNAL Counter : std_logic_vector(3 DOWNTO 0);
    SIGNAL CNT_CONTROL : std_logic_vector(8 DOWNTO 0);
    SIGNAL SDA_OE : std_logic;
    SIGNAL INTERRUPT : std_logic;
    SIGNAL nSDA_temp : std_logic;
    SIGNAL READOUT_internode : std_logic;
    SIGNAL D_OUT_temp : std_logic_vector(4 DOWNTO 0);
    SIGNAL Start : std_logic;
    SIGNAL Stop : std_logic;
    SIGNAL StartorStop_temp : std_logic;
    SIGNAL nStartorStop_temp : std_logic;


    BEGIN

    D_OUT <= D_OUT_temp;
    nSDA_temp <= NOT SDA;
    StartorStop_OUT <= StartorStop_temp;
    INTERRUPT_OUT <= INTERRUPT;


    PROCESS (RST, SCL)
    VARIABLE PresentState_temp : state;
    BEGIN
    IF (RST = '1') THEN
    PresentState_temp := IdleState;
    ELSIF (RISING_EDGE(SCL)) THEN
    PresentState_temp := Next_State;
    END IF;
    Present_State <= PresentState_temp;
    END PROCESS;


    PROCESS(RST,SDA,SCL)
    BEGIN
    IF (RST = '1') THEN
    Start <= '0';
    ELSIF (FALLING_EDGE(SDA)) THEN
    IF (SCL = '1') THEN
    Start <= '1';
    ELSE
    Start <= '0';
    END IF;
    END IF;
    END PROCESS;


    PROCESS(RST,SDA,SCL)
    BEGIN
    IF (RST = '1') THEN
    Stop <= '0';
    ELSIF (RISING_EDGE(SDA)) THEN
    IF (SCL = '1') THEN
    Stop <= '1';
    ELSE
    Stop <= '0';
    END IF;
    END IF;
    END PROCESS;


    PROCESS (Present_State, StartorStop_temp, Counter)
    VARIABLE NextState_temp : state;
    BEGIN
    CASE Present_State IS
    WHEN IdleState =>
    IF (StartorStop_temp = '1') THEN
    NextState_temp := AddressState;
    ELSE
    NextState_temp := IdleState;
    END IF;
    WHEN AddressState =>
    IF (StartorStop_temp = '0') THEN
    NextState_temp := IdleState;
    ELSE
    IF (Counter = "1000") THEN
    NextState_temp := AckState;
    ELSE
    NextState_temp := AddressState;
    END IF;
    END IF;
    WHEN AckState =>
    IF (StartorStop_temp = '0') THEN
    NextState_temp := IdleState;
    ELSIF (Counter = "1000") THEN
    NextState_temp := DataState;
    END IF;
    WHEN DataState =>
    IF (StartorStop_temp = '0') THEN
    NextState_temp := IdleState;
    ELSE
    IF (Counter = "1000") THEN
    NextState_temp := AckState;
    ELSE
    NextState_temp := DataState;
    END IF;
    END IF;
    END CASE;
    Next_State <= NextState_temp;
    END PROCESS;

    PROCESS (RST, Stop, StartorStop_temp, INTERRUPT, SCL)
    VARIABLE Counter_temp : std_logic_vector(3 DOWNTO 0);
    VARIABLE D_BUFFER_temp : std_logic_vector(7 DOWNTO 0);
    BEGIN
    IF (RST = '1') OR (Stop = '1') THEN
    Counter_temp := "1000";
    D_BUFFER_temp := "00000000";
    ELSIF (RISING_EDGE(SCL)) THEN
    IF (StartorStop_temp = '1') THEN
    CASE Present_State IS
    WHEN IdleState =>
    Counter_temp := Counter_temp - "0001";
    D_BUFFER_temp := D_BUFFER(6 DOWNTO 0) & SDA;
    WHEN AddressState =>
    IF (Counter_temp /= "0000") AND (Counter_temp <=
    "1000") THEN
    Counter_temp := Counter_temp - "0001";
    D_BUFFER_temp := D_BUFFER_temp(6 DOWNTO 0) &
    SDA;
    ELSIF (Counter_temp = "0000") THEN
    Counter_temp := "1000";
    END IF;
    WHEN AckState =>
    Counter_temp := Counter_temp - "0001";
    D_BUFFER_temp := D_BUFFER(6 DOWNTO 0) & SDA;
    WHEN DataState =>
    IF (Counter_temp /= "0000") AND (Counter_temp <=
    "1000") THEN
    Counter_temp := Counter_temp - "0001";
    D_BUFFER_temp := D_BUFFER_temp(6 DOWNTO 0) & SDA;
    ELSIF (Counter_temp = "0000") THEN
    Counter_temp := "1000";
    END IF;
    END CASE;
    END IF;
    END IF;
    Counter <= Counter_temp;
    D_BUFFER <= D_BUFFER_temp;
    END PROCESS;

    PROCESS (RST, SCL)
    VARIABLE SDA_OE_Enable : std_logic;
    VARIABLE READOUT_temp : std_logic;
    BEGIN
    IF (RST = '1') THEN
    SDA_OE_Enable := '0';
    READOUT_temp := '0';
    ELSIF (FALLING_EDGE(SCL)) THEN
    IF (StartorStop_temp = '1') THEN
    CASE Present_State IS
    WHEN IdleState =>
    SDA_OE_Enable := '0';
    READOUT_temp := '0';
    WHEN AddressState =>
    IF (Counter = "0000") THEN
    IF (D_BUFFER = "11111110") THEN
    SDA_OE_Enable := '0';
    ELSE
    SDA_OE_Enable := '1';
    END IF;
    END IF;
    WHEN AckState =>
    SDA_OE_Enable := '0';
    READOUT_temp := '0';
    WHEN DataState =>
    IF (Counter = "0000") THEN
    READOUT_temp := '1';
    SDA_OE_Enable := '0';
    ELSE
    READOUT_temp := '0';
    END IF;
    END CASE;
    END IF;
    END IF;
    SDA_OE <= SDA_OE_Enable;
    READOUT_internode <= READOUT_temp;
    END PROCESS;

    PROCESS(RST, Stop, StartorStop_temp, READOUT_internode, CNT_CONTROL,
    D_BUFFER)
    BEGIN
    IF (RST = '1') OR (Stop = '1') THEN
    CNT_CONTROL <= "000000000";
    INTERRUPT <= '0';
    ELSIF (RISING_EDGE(READOUT_internode)) THEN
    CNT_CONTROL <= CNT_CONTROL + 1;
    ELSE
    CNT_CONTROL <= CNT_CONTROL;
    END IF;
    IF (READOUT_internode = '1' AND Counter = 8 AND CNT_CONTROL = 1) THEN
    IF (D_BUFFER = "11111110") THEN
    INTERRUPT <= '0';
    ELSE
    INTERRUPT <= '1';
    END IF;
    END IF;
    IF (CNT_CONTROL >= 2) THEN
    READOUT <= READOUT_internode;
    ELSE
    READOUT <= '0';
    END IF;
    END PROCESS;

    PROCESS(RST,Start,Stop)
    BEGIN
    IF (RST = '1') THEN
    StartorStop_temp<='0';
    ELSE
    IF (Start = '1') THEN
    StartorStop_temp <= '1';
    ELSIF StartorStop_temp = '1' THEN
    IF (Stop = '1') OR (INTERRUPT = '1') THEN
    StartorStop_temp <= '0';
    END IF;
    END IF;
    END IF;
    END PROCESS;

    SDA <= SDA WHEN (SDA_OE) = '1' ELSE 'Z' ;
    D_OUT_temp(4 DOWNTO 0) <= D_BUFFER(7 DOWNTO 3) ;

    END i2c;
     
    underground, Jul 19, 2004
    #3
  4. underground

    asicbaba Guest

    Re: Does anyone have the I2C vhdl code and work for Altera Flex1

    So your requirement is to make this work....i could see couple of
    things going wrong at many places. just send me the test benches on
    which you are tesing i will get you the solution. YOU COULD MAIL ME AT




    "underground" <> wrote in message news:<>...
    > My code was described below..
    > I have already confused with my code,so if you can modify it then I will
    > appreciate you very much....
    > But how do I post my waveform(has already been saved in JPG)
    > with my reply in this web? or Do you mind to give me you email address?
    > underground
    > ___________________________________________________________
    >
    > LIBRARY ieee;
    > USE ieee.std_logic_1164.all;
    > USE ieee.std_logic_arith.all;
    > USE ieee.std_logic_unsigned.all;
    >
    > ENTITY i2c_integration IS
    > PORT (
    > SDA : INOUT std_logic;
    > SCL : IN std_logic;
    > RST : IN std_logic;
    > READOUT : OUT std_logic;
    > D_OUT : OUT std_logic_vector(4 DOWNTO 0);
    > StartOrStop_OUT : OUT std_logic;
    > INTERRUPT_OUT : OUT std_logic
    > );
    > END i2c_integration;
    >
    > ARCHITECTURE i2c OF i2c_integration IS
    >
    >
    > TYPE state IS (IdleState, AddressState, AckState, DataState);
    > SIGNAL Present_State : state;
    > SIGNAL Next_State : state;
    > SIGNAL D_BUFFER : std_logic_vector(7 DOWNTO 0);
    > SIGNAL Counter : std_logic_vector(3 DOWNTO 0);
    > SIGNAL CNT_CONTROL : std_logic_vector(8 DOWNTO 0);
    > SIGNAL SDA_OE : std_logic;
    > SIGNAL INTERRUPT : std_logic;
    > SIGNAL nSDA_temp : std_logic;
    > SIGNAL READOUT_internode : std_logic;
    > SIGNAL D_OUT_temp : std_logic_vector(4 DOWNTO 0);
    > SIGNAL Start : std_logic;
    > SIGNAL Stop : std_logic;
    > SIGNAL StartorStop_temp : std_logic;
    > SIGNAL nStartorStop_temp : std_logic;
    >
    >
    > BEGIN
    >
    > D_OUT <= D_OUT_temp;
    > nSDA_temp <= NOT SDA;
    > StartorStop_OUT <= StartorStop_temp;
    > INTERRUPT_OUT <= INTERRUPT;
    >
    >
    > PROCESS (RST, SCL)
    > VARIABLE PresentState_temp : state;
    > BEGIN
    > IF (RST = '1') THEN
    > PresentState_temp := IdleState;
    > ELSIF (RISING_EDGE(SCL)) THEN
    > PresentState_temp := Next_State;
    > END IF;
    > Present_State <= PresentState_temp;
    > END PROCESS;
    >
    >
    > PROCESS(RST,SDA,SCL)
    > BEGIN
    > IF (RST = '1') THEN
    > Start <= '0';
    > ELSIF (FALLING_EDGE(SDA)) THEN
    > IF (SCL = '1') THEN
    > Start <= '1';
    > ELSE
    > Start <= '0';
    > END IF;
    > END IF;
    > END PROCESS;
    >
    >
    > PROCESS(RST,SDA,SCL)
    > BEGIN
    > IF (RST = '1') THEN
    > Stop <= '0';
    > ELSIF (RISING_EDGE(SDA)) THEN
    > IF (SCL = '1') THEN
    > Stop <= '1';
    > ELSE
    > Stop <= '0';
    > END IF;
    > END IF;
    > END PROCESS;
    >
    >
    > PROCESS (Present_State, StartorStop_temp, Counter)
    > VARIABLE NextState_temp : state;
    > BEGIN
    > CASE Present_State IS
    > WHEN IdleState =>
    > IF (StartorStop_temp = '1') THEN
    > NextState_temp := AddressState;
    > ELSE
    > NextState_temp := IdleState;
    > END IF;
    > WHEN AddressState =>
    > IF (StartorStop_temp = '0') THEN
    > NextState_temp := IdleState;
    > ELSE
    > IF (Counter = "1000") THEN
    > NextState_temp := AckState;
    > ELSE
    > NextState_temp := AddressState;
    > END IF;
    > END IF;
    > WHEN AckState =>
    > IF (StartorStop_temp = '0') THEN
    > NextState_temp := IdleState;
    > ELSIF (Counter = "1000") THEN
    > NextState_temp := DataState;
    > END IF;
    > WHEN DataState =>
    > IF (StartorStop_temp = '0') THEN
    > NextState_temp := IdleState;
    > ELSE
    > IF (Counter = "1000") THEN
    > NextState_temp := AckState;
    > ELSE
    > NextState_temp := DataState;
    > END IF;
    > END IF;
    > END CASE;
    > Next_State <= NextState_temp;
    > END PROCESS;
    >
    > PROCESS (RST, Stop, StartorStop_temp, INTERRUPT, SCL)
    > VARIABLE Counter_temp : std_logic_vector(3 DOWNTO 0);
    > VARIABLE D_BUFFER_temp : std_logic_vector(7 DOWNTO 0);
    > BEGIN
    > IF (RST = '1') OR (Stop = '1') THEN
    > Counter_temp := "1000";
    > D_BUFFER_temp := "00000000";
    > ELSIF (RISING_EDGE(SCL)) THEN
    > IF (StartorStop_temp = '1') THEN
    > CASE Present_State IS
    > WHEN IdleState =>
    > Counter_temp := Counter_temp - "0001";
    > D_BUFFER_temp := D_BUFFER(6 DOWNTO 0) & SDA;
    > WHEN AddressState =>
    > IF (Counter_temp /= "0000") AND (Counter_temp <=
    > "1000") THEN
    > Counter_temp := Counter_temp - "0001";
    > D_BUFFER_temp := D_BUFFER_temp(6 DOWNTO 0) &
    > SDA;
    > ELSIF (Counter_temp = "0000") THEN
    > Counter_temp := "1000";
    > END IF;
    > WHEN AckState =>
    > Counter_temp := Counter_temp - "0001";
    > D_BUFFER_temp := D_BUFFER(6 DOWNTO 0) & SDA;
    > WHEN DataState =>
    > IF (Counter_temp /= "0000") AND (Counter_temp <=
    > "1000") THEN
    > Counter_temp := Counter_temp - "0001";
    > D_BUFFER_temp := D_BUFFER_temp(6 DOWNTO 0) & SDA;
    > ELSIF (Counter_temp = "0000") THEN
    > Counter_temp := "1000";
    > END IF;
    > END CASE;
    > END IF;
    > END IF;
    > Counter <= Counter_temp;
    > D_BUFFER <= D_BUFFER_temp;
    > END PROCESS;
    >
    > PROCESS (RST, SCL)
    > VARIABLE SDA_OE_Enable : std_logic;
    > VARIABLE READOUT_temp : std_logic;
    > BEGIN
    > IF (RST = '1') THEN
    > SDA_OE_Enable := '0';
    > READOUT_temp := '0';
    > ELSIF (FALLING_EDGE(SCL)) THEN
    > IF (StartorStop_temp = '1') THEN
    > CASE Present_State IS
    > WHEN IdleState =>
    > SDA_OE_Enable := '0';
    > READOUT_temp := '0';
    > WHEN AddressState =>
    > IF (Counter = "0000") THEN
    > IF (D_BUFFER = "11111110") THEN
    > SDA_OE_Enable := '0';
    > ELSE
    > SDA_OE_Enable := '1';
    > END IF;
    > END IF;
    > WHEN AckState =>
    > SDA_OE_Enable := '0';
    > READOUT_temp := '0';
    > WHEN DataState =>
    > IF (Counter = "0000") THEN
    > READOUT_temp := '1';
    > SDA_OE_Enable := '0';
    > ELSE
    > READOUT_temp := '0';
    > END IF;
    > END CASE;
    > END IF;
    > END IF;
    > SDA_OE <= SDA_OE_Enable;
    > READOUT_internode <= READOUT_temp;
    > END PROCESS;
    >
    > PROCESS(RST, Stop, StartorStop_temp, READOUT_internode, CNT_CONTROL,
    > D_BUFFER)
    > BEGIN
    > IF (RST = '1') OR (Stop = '1') THEN
    > CNT_CONTROL <= "000000000";
    > INTERRUPT <= '0';
    > ELSIF (RISING_EDGE(READOUT_internode)) THEN
    > CNT_CONTROL <= CNT_CONTROL + 1;
    > ELSE
    > CNT_CONTROL <= CNT_CONTROL;
    > END IF;
    > IF (READOUT_internode = '1' AND Counter = 8 AND CNT_CONTROL = 1) THEN
    > IF (D_BUFFER = "11111110") THEN
    > INTERRUPT <= '0';
    > ELSE
    > INTERRUPT <= '1';
    > END IF;
    > END IF;
    > IF (CNT_CONTROL >= 2) THEN
    > READOUT <= READOUT_internode;
    > ELSE
    > READOUT <= '0';
    > END IF;
    > END PROCESS;
    >
    > PROCESS(RST,Start,Stop)
    > BEGIN
    > IF (RST = '1') THEN
    > StartorStop_temp<='0';
    > ELSE
    > IF (Start = '1') THEN
    > StartorStop_temp <= '1';
    > ELSIF StartorStop_temp = '1' THEN
    > IF (Stop = '1') OR (INTERRUPT = '1') THEN
    > StartorStop_temp <= '0';
    > END IF;
    > END IF;
    > END IF;
    > END PROCESS;
    >
    > SDA <= SDA WHEN (SDA_OE) = '1' ELSE 'Z' ;
    > D_OUT_temp(4 DOWNTO 0) <= D_BUFFER(7 DOWNTO 3) ;
    >
    > END i2c;
     
    asicbaba, Jul 20, 2004
    #4
  5. underground

    underground Guest

    Re: Does anyone have the I2C vhdl code and work for Altera Flex1

    Dear Nicolas:
    I had already send the compressed rar file to you yesterday.
    Do you receive it?
    If you have already received it,then please let me know.
    (Reply to me for acknowledgement.)
    Your help will be appreciated.

    Underground
     
    underground, Jul 22, 2004
    #5
  6. underground

    underground Guest

    Re: Does anyone have the I2C vhdl code and work for Altera Flex1

    Dear Asicbaba:
    I had already send the compressed rar file to you yesterday.
    Do you receive it?
    If you have already received it,then please let me know.
    (Reply to me for acknowledgement.)
    Your help will be appreciated.

    Underground
     
    underground, Jul 22, 2004
    #6
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