filters in vhdl

  • Thread starter Frank van Eijkelenburg
  • Start date
F

Frank van Eijkelenburg

I've to implement a kind of filter in vhdl. The incoming datastream must
pass a (-1 0 2 0 -1) filter. Are there some examples for such a lineair
filters? Can anyone point me into the right direction?

TIA,
Frank
 
F

FE

Frank,
I don't know if it's that you want but bellow you can found different
implementation form of your filter at data incoming full clock speed (1 new
filtered data output at each clk cycle).

(Please view in fixed-width font, e.g. Courier)
[Rn] is a register
(+) is an adder
(-) is a subtractor
(2x) is multiply by 2 (shift left by 1)
(/4) is divide by 4

Standard form: FIR Bandpass [-1 0 2 0 -1]/4
Group delay = 2
Pipeline delay = 1
Total delay = 3
in--+-[R0]--[R1]-+-[R2]--[R3]-+
| | |
| +--------|------------+
| | |
| | (2x)
| | |
+--(+)------(-)--(/4)--|R4|--out

Standard form: FIR Bandpass [-1 0 2 0 -1]/4
Group delay = 2
Pipeline delay = 2
Total delay = 4
in--+-[R0]--[R1]--[R2]-+-[R3]-+
| | |
| +--------------|------+
| | |
| | (2x)
| | |
+--(+)--[R4]------(-)--(/4)--[R5]--out

Transpose form: FIR Bandpass [-1 0 2 0 -1]/4
Group delay = 2
Pipeline delay = 1
Total delay = 3
in--+--------------+----------------+
| | |
| (2x) |
| | |
+-[R0]--[R1]--(-)--[R2]--[R3]--(-)--(/4)--[R4]--out

regards
fe
 

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