Finding maximum clock rate

Discussion in 'VHDL' started by Stephen Coe, May 16, 2004.

  1. Stephen Coe

    Stephen Coe Guest

    Hi,

    I am new to Xilinx ISE and I am wondering how to determine the maximum
    delay, the maximum allowable clock rate for a design.

    Is there also a way to determine what is causing this maximum delay?

    Steve
     
    Stephen Coe, May 16, 2004
    #1
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