Finding MSB in a std_logic_vector

[Aiken]

data_in : in std_logic_vector(data_size-1 downto 0)
data_out: out std_logic_vector((log2(data_size downto 0)

If the input vector is "000110101", then output is "101" = 5

I don't want to use one case statement to due with it (since it will
create not balance logic)
How can I code it to have balance combination logic and minimize the
level of logic.

p.s. no register in the desin

 

[Mike Treseler]

data_in : in std_logic_vector(data_size-1 downto 0)
data_out: out std_logic_vector((log2(data_size downto 0)

If the input vector is "000110101", then output is "101" = 5

I would load a counter variable with 8
and a shifter variable with the input vector
then loop a shift left and a decrement until I saw a one.

I don't want to use one case statement to due with it (since it will
create not balance logic)
How can I code it to have balance combination logic and minimize the
level of logic.

That is academic

p.s. no register in the design

That is unfortunate.
The loop would have to be an unclocked FOR.

-- Mike Treseler

 

[KJ]

data_in : in std_logic_vector(data_size-1 downto 0)
data_out: out std_logic_vector((log2(data_size downto 0)

If the input vector is "000110101", then output is "101" = 5

The MSB of a vector is equal to the log2 of that vector

data_out <= std_logic_vector(log2(unsigned(data_in)));

Google for the synthesizable code that implement log2.

Kevin Jennings

 

[Charles Gardiner]

How about something like this?

function get_vector_msb(p1 : std_logic_vector) return natural is
variable v_search_vector : std_logic_vector(p1'length -1 downto 0);
begin
v_search_vector := p1;
for i in v_search_vector'left downto 0 loop
if (v_search_vector(i) = '1') then
return i;
end if;
end loop;
return 0;
end function;

and then in your code,
Use IEEE.numeric_std.all;
. . . . . .
sig_name <= std_logic_vector(to_unsigned(get_vector_msb(input_vector),
sig_name'length));

It should synthesise to an and-or array, boolean optimised by synthesis.

BTW as far as I'm aware there will be a function find_leftmost() in VHDL
2006 or sometime later.

 

[jeppe]

Well I believe your looking for a "priority encoder" -
Please search the net yourself or tjek this site:

http://tams-www.informatik.uni-hamb...webdemos/10-gates/45-priority/priority83.html

"pure" combinatorial logic - no registers involved.

Jeppe

 

[jeppe]

Try this code - may be must you adjust the code for your needs.
Your welcome
Jeppe

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity PrioEncoder is
	Generic( N:       Natural := 8;
	          Log2N:  Natural := 3);
	Port (  Data_in : in   STD_LOGIC_VECTOR (N downto 0);
		    Data_out : out  STD_LOGIC_VECTOR (Log2N downto 0));
end PrioEncoder;

architecture Behavioral of PrioEncoder is

begin

	This_will_synthesize_into_combinatorial_logic:
	process( Data_in)
		variable i,Count: integer range -1 to N;
	begin
		Count := N;
		while Count>=0 loop
			exit when Data_in( Count)='1';
			Count := Count-1;
		end loop;
		Data_out <= Conv_std_logic_vector( Count,Log2N+1);
	end process;
end Behavioral;

 

[Brad Smallridge]

p.s. no register in the desin

It seems you should start with a row
of OR gates starting with the MSB and
serializing down to the LSB. The output
of those serial gates are easier to decode
into binary.

SERIAL GATE POSITION
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 1 0 0 1
0 0 0 0 0 1 1 0 1 0
0 0 0 0 1 1 1 0 1 1
0 0 0 1 1 1 1 1 0 0
0 0 1 1 1 1 1 1 0 1
0 1 1 1 1 1 1 1 1 0
1 1 1 1 1 1 1 1 1 1

I'm not sure how to code this in the generic
form but there is a relatively simple pattern.

POSITION(0)<= S(7) or
(S(5) and not S(6))or
(S(3) and not S(4))or
(S(1) and not S(2) ;

POSITION(1)<=
S(7) or S(6) or
((S(2) or S(3)) and not(S(5) or S(6))) ;

POSITION(2)<=
S(7) or S(6) or S(5) or S(4) ;

This logic creates a 000 output when the
input is all zeroes whereas your original
post is not clear how to distinguish a
0000000 from a 0000001 input.

Brad Smallridge
AiVision