fixed point multiplier in VHDL

Discussion in 'VHDL' started by Viswan, Feb 1, 2004.

  1. Viswan

    Viswan Guest


    I have to design a processor in VHDL which does various
    multiplications and divisions to find a result which is a real number.
    As it is a hand held low power device I decided to use fixed point
    arithmetic for all the arithmetic operations involved in the design of
    the processor.

    I would like to know the best way to design the low power processor in
    VHDL. How could I implement fixed point multiplication and division
    in VHDL? Can I use * operator? Or is it better to use some other
    algorithms for multiplications for low power processor?

    Any help in this issue is greatly appreciated.

    Viswan, Feb 1, 2004
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  2. 1. Write code.
    2. Sim code.
    3. Select device
    4. Synth code.
    Consider using the IEEE.NUMERIC_STD library and work with vectors
    (type SIGNED or UNSIGNED) that are any size you like.
    Let the synth have a go at it first.

    -- Mike Treseler
    Mike Treseler, Feb 1, 2004
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  3. Viswan

    Jez Smith Guest

    It all depends on how fast you want to produce the results of your
    multiplication,you could use the standard '*' operator and run the clock
    very slowly.we really need more information.
    Jez Smith, Feb 2, 2004
  4. Viswan

    Jeroen Guest

    you could enter something like 'multiplier fpga' in Google and enough hits
    come up that should point you in the right direction.

    Jeroen, Feb 3, 2004
  5. Viswan wrote:

    First, you should implement everthing with the simple * operator. If it
    does not fit your constraints, you should look for different algorithms.

    Often synthesis tools implement Carry-Save-Arrays (simplest), Wallace
    Trees or Booth-Wallace-Trees. (Synopsys DesignWare(Foundation): CSA,
    NBW, WALL) All these Variants are quite good in terms of power are and
    speed - if you choose area-optimisazion for synthesis.

    Faster than a CSA is a LeapfrogCSA (LFCSA) with similar structure.

    Speed mosty depends on the final Carry Propagate Adder (CPA). A
    Carry-Ribble-Adder is very slow, but has for low bitwidths (e.g. 16*16
    Bits) often the lowest power.
    Much faster and only a little bit worse than CRA in therms of power are
    fast adders, like CLA, CSA... (let the synthesis build them - doing it
    manually with algorithms like GEF (generalized earliest first) leads to
    a little bit slower results, but mostly a little bit smaller area - a
    too small improvement).

    Forget SignedDigit multipliers as a replacement for standart multipliers
    for low to medium bitwidths. They are much bigger, slower and consume
    more power than standart multipliers. But think about them, if your
    complete signal path fits SignedDigit arithmetic.

    Ralf Hildebrandt, Feb 3, 2004
  6. Viswan

    Sandeep Guest

    You could also use the '*' operator and provide extra pipeline stages
    at the output of the multiply and some synthesis tools (for e.g
    Synplify) will use the registers to implement a pipelined multiplier
    rather than pure combinatorial logic with delays at the output. You
    could control the pipeline for the speed of operation you need.

    Sandeep, Feb 3, 2004
  7. Viswan

    Ray Andraka Guest

    You don't provide nearly enough information. An AND gate is a 1 bit by 1
    bit fixed point multiply. It also depends on your target technology, how
    many clocks per product you have to work with, among other things. For
    small multiplies, a look-up table might be best. For larger ones there
    are many approaches, not all of which are appropriate for all

    --Ray Andraka, P.E.
    President, the Andraka Consulting Group, Inc.
    401/884-7930 Fax 401/884-7950

    "They that give up essential liberty to obtain a little
    temporary safety deserve neither liberty nor safety."
    -Benjamin Franklin, 1759
    Ray Andraka, Feb 4, 2004
  8. Viswan

    Viswan Guest

    Thanks for responding.

    I have to design a processor that can be used in a hand held device. I
    have to develop a code and synthesize it on to FPGA. As I told already
    my design involves many multiplications, divisions, additions and
    substratctions. As all those are real numbers, an integer arithmetic
    unit is not sufficient. So I decided to use either fixed point
    arithmetic or floating point arithmetic. I had a problem in finding
    out which arithmetic is best suited for low power applications. I
    assumed fixed point arithmetic is better as it uses low complex data
    path. I would like to know how it could be implemented for real
    numbers in VHDL.

    I have another question. Is the core generated arithmetic circuits (
    optimised for area) are useful for these kind of applications? I
    really donot have any idea regarding all these as I am new to VHDL.

    Thanks a lot for your suggestions
    Viswan, Feb 9, 2004
  9. Some devices have canned multiplier blocks. Some don't.
    Some synthesizers work better than others.
    Vendor-specific cores are harder to simulate than synth code.
    Try it both ways and decide for yourself.

    -- Mike Treseler
    Mike Treseler, Feb 9, 2004
  10. Viswan

    Ray Andraka Guest

    You need to do a numerical analysis of your design to determine things like dynamic range, scaling
    at each node in your process, and required precision. For problems with a small dynamic range, it
    doesn't make sense to use floating point. Applications that need a large dynamic range may benefit
    from less hardware by using floating point. You'll also want to examine the algorithm carefully to
    see if there are any rearrangements or alternative approaches to reduce the amount of division
    operations, and possibly the same for multiplication. Division is both time and resource intensive
    to implement in hardware. Above all, remember that VHDL is a hardware description language, not a
    programming language. To be successful, you should visualize the hardware required to address your
    application, then write the VHDL to describe that hardware. A common mistake is to write your VHDL
    as if it were a programming language with no thought as to what the resulting hardware looks like.
    --Ray Andraka, P.E.
    President, the Andraka Consulting Group, Inc.
    401/884-7930 Fax 401/884-7950

    "They that give up essential liberty to obtain a little
    temporary safety deserve neither liberty nor safety."
    -Benjamin Franklin, 1759
    Ray Andraka, Feb 11, 2004
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