Floating point division

Discussion in 'VHDL' started by Pieter Hulshoff, Dec 5, 2004.

  1. Hello all,

    I'm facing the all-time favorite design issue of creating an implementation
    for floating point division (for hobby, not work). A direct face value
    implementation shouldn't cause too much trouble, but I wonder if anyone
    knows some optimized algorithms for this problem.

    Also: part of the division always seems to be the (18-22 bit in this case)
    subtraction. One clock subtraction of such numbers should probably work at
    most at 100-150 MHz. Should I consider breaking up the subtraction into 2
    clock cycles, or are there better algorithms for this that use a lower
    logic depth? Are compilers like Synopsys DC capable of optimizing this or
    should I delve into subtraction algorithms myself?


    Pieter Hulshoff
    Pieter Hulshoff, Dec 5, 2004
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  2. Pieter Hulshoff

    David Bishop Guest

    Floating point division is something supported by the new IEEE floating
    point packages:
    The wonderful thing about floating point is that you can assume that
    there is a "1" in the MSB of the divisor. This means that you can cut
    the size of your subtraction tree in half.

    I have already written an algorithm to do this dynamically for a
    floating point number.
    David Bishop, Dec 7, 2004
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  3. Interesting, but which tools are capable of creating good hardware out of
    the functions in these packages, and how optimal are these?
    I'm certainly interested in seeing this algorithm sometime. What we're
    currently considering is dropping the division, and implement a simple 1/1.m
    algorithm combined with a multiplier (which we need anyway). The 1/1.m can
    easily be implemented with the use of a LUT for the higher bits of the
    mantissa, and interpolation for the lower bits. The results we're getting
    sofar seem promising.


    Pieter Hulshoff
    Pieter Hulshoff, Dec 7, 2004
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