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- Oct 18, 2007
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can we assign a output as a real number?
can we assign a real signal to the outputs how to assign?
entity sreal is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out --------); ---we should be the type
end sreal;
architecture Behavioral of sreal is
signal d,f,g:real;
begin
d<=0.001;
f<=d*0.2569;
g<=f*10000.0;
c<=g;---how to assign g to the c
end Behavioral;
---the code can not be sysnthesised can u give the correction in the code..
can we assign a real signal to the outputs how to assign?
entity sreal is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out --------); ---we should be the type
end sreal;
architecture Behavioral of sreal is
signal d,f,g:real;
begin
d<=0.001;
f<=d*0.2569;
g<=f*10000.0;
c<=g;---how to assign g to the c
end Behavioral;
---the code can not be sysnthesised can u give the correction in the code..