how to produce 20MHz from 100MHz
this is my current code, that divides 100MHz to 10Mhz, i'm finding it hard to recode it in such a way that it will produce 20Mhz.
can anyone help me out?
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- This clock divider circuit outputs a frequency equal to 100MHz?
entity freqdiv is
Port ( clk_in : in std_logic;
res : in std_logic;
div10out : out std_logic);
end freqdiv;
architecture Behavioral of freqdiv is
component div10
Port ( clk : in std_logic;
res : in std_logic;
div2out : out std_logic);
end component;
begin
u1: div10 port map (clk_in,res,div10out); --10MHz
end Behavioral;
--subcomponent responsible for frequency division/counter
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity div10 is
Port ( clk : in std_logic;
res : in std_logic;
div2out : out std_logic);
end div10;
architecture Behavioral of div10 is
signal cntr : std_logic_vector (3 downto 0);
begin
process (clk, res)
begin
if res = '1' then
cntr <= "0000";
div2out <= '0';
else
if clk'event and clk = '0' and res ='0' then
cntr <= cntr + 1;
if cntr = "0100" then
div2out <= '1';
end if;
if cntr = "1001" then
div2out <= '0';
cntr <= "0000";
end if;
end if;
end if;
end process;
end Behavioral;