generate sequential logic with a function or a procedure call

[midiwidi]

Hallo

There are VHDL modules that I offen need in my designs for example a
sync module. It generates a puls with the length of one clk periode, if
there is an edge on its input.

-- syncrise.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity syncrise is
port( clk: in std_logic;
nres: in std_logic;
input: in std_logic;
output: out std_logic
);
end syncrise;

architecture behavioral of syncrise is
signal stage: std_logic_vector(1 downto 0);
begin
process (clk,nres,input)
begin
if (nres = '0') then
output <= '0';
stage <= "00";
elsif (clk'event and clk = '1') then
stage <= stage(0) & input;
if stage = "01" then
output <= '1';
else
output <= '0';
end if;
end if;
end process;
end behavioral;

Is there any possebility to use this module like a function or
procedure ?
like a <= syncrise(b); or syncrise(a,b);
Or is it not possible to produce sequential hardware with a function or
procedure call?
Any other ideas to do this?

 

[Amal]

Normally you can create synchronous logic using procedures. But the
problem in this case is that VHDL (I do not know about VHDL-200x) does
not support signal declatrations (similar to static variables is C)
inside a VHDL procedure. Therfore you won't be able to declare signal
stage inside the procdure. Otherwise you could do something like this:

procedure syncrise(
signal clk : in std_logic;
constant nres : in std_logic;
constant input : in std_logic;
signal output : out std_logic
) is
signal stage : std_logic_vector(1 downto 0);
begin
if (nres = '0') then
output <= '0';
stage <= "00";
elsif ( clk'event and clk = '1' ) then
stage <= stage(0) & input;
if stage = "01" then
output <= '1';
else
output <= '0';
end if;
end if;
end procedure syncrise;

And call it like:

syncrise( clock, reset_n, a, b );

This won't compile, but in many simple cases, like flip-flops, you can
use this method. Exemplar uses this in its libraries. They declare
many DFF primitives as procedures.

-- Amal

 

[jens]

You can create a component, which will allow you to hide any
intermediate signals & registers, in addition to allowing use of
generics to specify which edge(s) to detect or whether the input is
synchronous or asynchronous.

 

[Mike Treseler]

There are VHDL modules that I offen need in my designs for example a
sync module. It generates a puls with the length of one clk periode, if
there is an edge on its input.

See the procedure "rising"
in the rising level counter source here:
http://home.comcast.net/~mike_treseler/

-- Mike Treseler

 

[midiwidi]

Thanks for your answers. I've tried Mikes version and it works. That is
what I was looking for.

Best reguards
Markus

 

[Amal]

Interesting method. So basically, the same procedure that I wrote
before becomes:

architecture rtl of test is

type storageT is record
output : std_logic;
stage : std_logic_vector(1 downto 0);
end record;

procedure syncrise(
signal clk : in std_logic;
constant nres : in std_logic;
constant input : in std_logic;
signal io : inout storageT
) is
begin
if (nres = '0') then
io.output <= '0';
io.stage <= "00";
elsif ( clk'event and clk = '1' ) then
io.stage <= io.stage(0) & input;
if io.stage = "01" then
io.output <= '1';
else
io.output <= '0';
end if;
end if;
end procedure syncrise;

signal clk : std_logic;
signal nres : std_logic;

signal a : std_logic;
signal b : storageT;

begin

syncrise( clk, nres, a, b );

end;

 

[Mike Treseler]

Normally you can create synchronous logic using procedures. But the
problem in this case is that VHDL (I do not know about VHDL-200x) does
not support signal declatrations (similar to static variables is C)
inside a VHDL procedure.

True, but that is a good thing.
Signals are only really needed to wire instances together.
The concurrent procedure call is really an instance, not a procedure.
see: http://groups.google.com/groups?q=vhdl+concurrent+procedure+call

A procedure declaration between the synthesis process IS and BEGIN
has access to all of the process variables and is truly procedural.
The advantage of a single process entity is that all process variables
have full scope and no signal declarations are necessary.

For an example, see the reference design source here:

http://home.comcast.net/~mike_treseler/

-- Mike Treseler

 

[Mike Treseler]

Interesting method. So basically, the same procedure that I wrote
before becomes:
architecture rtl of test is
type storageT is record
output : std_logic;
stage : std_logic_vector(1 downto 0);
end record;
procedure syncrise(

....

No. A sequential procedure has to be in process scope.
See my other postings in this thread.

-- Mike Treseler