generate statements

[rajan]

Dear colleagues,
I have a LUT (look-up-table) designed as an array (of switch cells) with the
GENERATE statement. I would like to know if there is any other method, which
is better than the method I applied below. However, the synthesis of the
code below doesn´t give a problem, but I want to know if we can improve it
further, or can put it another way.

ENTITY lut_cells IS
PORT (w_lut : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
en_lut: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
s_zero : IN STD_LOGIC);
END lut_cells;

ARCHITECTURE rtl OF lut_cells IS


TYPE store_t IS ARRAY (0 TO 4) OF STD_LOGIC_VECTOR (0 TO 7);
CONSTANT map_sig: store_t :=
("1001000",
"1101100",
"1111110",
"1111110");

TYPE en_store IS ARRAY (0 TO 4) OF STD_LOGIC_VECTOR (0 TO 7);

SIGNAL fec_map: en_store;
SIGNAL wire : STD_LOGIC_VECTOR (7 DOWNTO 0);

BEGIN


--------------- switch cells ------------------
enables:
FOR i IN 4 DOWNTO 0 GENERATE
switches:
FOR j IN 7 DOWNTO 0 GENERATE

switch_s0 :
IF map_sig(i)(j) = '0' GENERATE
s0 : sw1 PORT MAP (
D0 => s_zero,
D1 => wire(j),
Z => fec_map(i)(j));
END GENERATE switch_s0;

switch_s1 :
IF map_sig(i)(j) = '1' GENERATE
s1 : sw2 PORT MAP (
D0 => s_zero,
D1 => wire(j),
Z => fec_map(i)(j)
);
END GENERATE switch_s1;

END GENERATE;

-- enables --
en_lut(i) <= fec_map(i)(0) OR fec_map(i)(1) OR fec_map(i)(2) OR
fec_map(i)(3)
OR fec_map(i)(4) OR fec_map(i)(5) OR
fec_map(i)(6) OR fec_map(i)(7) ;

END GENERATE;

END rtl;

 

[Egbert Molenkamp]

Looks nice.
In stead of
en_lut(i) <= fec_map(i)(0) OR fec_map(i)(1) OR fec_map(i)(2) OR
fec_map(i)(3)
OR fec_map(i)(4) OR fec_map(i)(5) OR fec_map(i)(6)
OR fec_map(i)(7) ;

you could write:
en_lut(i) <= '1' WHEN fec_map(i)/=(fec_map(i)'range=>'0') ELSE '0';

or use an or_reduce function. This is not (yet) a standard IEEE function.
But in the meantime you can write your own or use the one from Ben Cohen:
http://members.aol.com/vhdlcohen/vhdl/Models.html and choose
numeric_more.zip

Egbert Molenkamp