Tom,
No. On the contrary, Confluence forces you to take an even closer
look at your hardware structures and the algorithms that generate
them.
I am glad to see we agree that you can't forget about
the hardware. When one forgets about the hardware, they
get what they deserve.
Once we figure out the nature of the hardware and what to
do for a fixed number of iterations it is fairly straight
forward to genericize it with VHDL.
The problematic places of this problem are the arbiter (select
active device) and the memory multiplexer (select address and
data to memory for the active device).
The arbiter has request and grant signals. Each of these can
use generics an array with the width that matches the number
of devices in the system. The width would be specified by
a generic.
The memory multiplexer is a little more tricky as the objects
that need to be multiplexed are the address and data busses.
We need a couple of types defined to be an unconstrained
array of an array type. One to hold address and one to hold
data.
At this point I think I have done enough of the homework
problem that was posted.
This is not just theoretically do-able in VHDL, I have done it.
It is not difficult, you just need to be organized and
structure the problem right (as you would have to do for any
solution - even confluence).
Expert Confluence and VHDL Training for Hardware Design and
Verification
Hart to tell. I am a strong typing fan. I don't like
debugging in the simulator - I prefer to debug in the
compiler.
Cheers,
Jim
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Jim Lewis
Director of Training mailto:
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SynthWorks Design Inc.
http://www.SynthWorks.com
1-503-590-4787
Expert VHDL Training for Hardware Design and Verification
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