vipinlal said:
this may help you..
vhdlguru.blogspot.com/2010/03/generics-in-vhdl-construction-of.html
help me!!!!!!!!!!!!!!!!!!!1
I design a n_bit register and in the design I use dffs (with use of port map and generic map). Also I write a package and I put all of my component declarations in it. Now I want write a test bench for this register. But my test bench has error, and doesn't know my generic variable.
--package declaration
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
PACKAGE basic_utility IS
COMPONENT dff
PORT(din,clk,rst:IN std_logic;
dout:OUT std_logic);
END COMPONENT;
COMPONENT reg_nb
GENERIC (length:natural);
PORT(reg_in:IN std_logic_vector(length DOWNTO 0);
clk,rst:IN std_logic;
reg_out:OUT std_logic_vector(length DOWNTO 0));
END COMPONENT;
END basic_utility;
--dff
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY dff IS
PORT(din,clk,rst:IN std_logic;
dout:OUT std_logic);
END dff;
ARCHITECTURE behavioral OF dff IS
BEGIN
process(clk)
BEGIN
IF (rst= '1')THEN
dout<='0';
ELSE
IF (clk='1' AND clk'event) THEN
dout<=din;
END IF;
END IF;
END PROCESS;
END behavioral;
--n bit register
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.basic_utility.ALL;
ENTITY reg_nb IS
GENERIC (length:natural);
PORT(reg_in:IN std_logic_vector(length DOWNTO 0);
clk,rst:IN std_logic;
reg_out:OUT std_logic_vector(length DOWNTO 0));
END reg_nb;
ARCHITECTURE structural OF reg_nb IS
BEGIN
reg:
FOR i IN length DOWNTO 0 GENERATE
DFF_units:dff
PORT MAP(din=>reg_in(i),clk=>clk,rst=>rst,dout=>reg_out(i));
END GENERATE;
END structural;
--test bench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.basic_utility.ALL;
ENTITY reg_nb_test IS
END reg_nb_test;
ARCHITECTURE test OF reg_nb_test IS
SIGNAL r_in: std_logic_vector(length DOWNTO 0);
SIGNAL r_out: std_logic_vector(length DOWNTO 0);
SIGNAL clk: std_logic :='0';
SIGNAL rst: std_logic:='1';
BEGIN
--Generate clock
clk<=NOT clk AFTER 10 ns;
rst<='0' AFTER 3ns;
r_in<="11110000" AFTER 15 ns;
reg1:reg_nb
GENERIC MAP(length=>7) PORT MAP(reg_in=>r_in,clk=>clk,rst=>rst,reg_out=>r_out);
END test;