Getting started with Altera IP Core

A

ALuPin

Hi,

I am trying to simulate the Example Instance of the Altera DDR SDRAM Controller
IP Core.

As described in the DDR SDRAM MegaCoreFunction User Guide
I type the following command under Modelsim
to simulate the IP functional simulation model.
set use_simgen_model 1
source example_controller_ddr_sdram_vsim.tcl

When running the tcl script I get error messages that several signals
are not found, for example:
# ** Error: No objects found matching "/DDR_SDRAM_top_tb/dut/local_rdata"
# Executing ONERROR command at macro ./wave.do line 35

What is going wrong ?

One additional question:

What is the difference if I simulate the pre-compiled ModelSim VHDL libraries
or if I simulate with an IP functional simulation model (DDR SDRAM MegaCore
Function UserGuide page 43) ?

Maybe someone has tried to get startet with the IP Core and has some
idea of what goes wrong ...

I am using QuartusII v. 4.1 SP1 and Modelsim Altera 5.8.c

Kind regards
 

Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments. After that, you can post your question and our members will help you out.

Ask a Question

Members online

Forum statistics

Threads
473,744
Messages
2,569,483
Members
44,903
Latest member
orderPeak8CBDGummies

Latest Threads

Top