Dimcliff said:
I'm a newbie in vhdl programming. But I have to make a gold code
generator in a xillinx fpga device.
That doesn't seem too difficult,
since the code is already written for you.
See pg 8 in
http://www.xilinx.com/bvdocs/appnotes/xapp217.pdf
Let's have a look at the unzipped files:
VSIM 7> vcom vhd_suba.vhd vhd_subb.vhd vhd_top.vhd
vcom vhd_suba.vhd vhd_subb.vhd vhd_top.vhd
# Model Technology ModelSim ALTERA vcom 6.0e Compiler 2005.06 Jun 18 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity lfsr_a
# -- Compiling architecture lfsr_a_arch of lfsr_a
# -- Compiling entity lfsr_b
# -- Compiling architecture lfsr_b_arch of lfsr_b
# -- Compiling entity gold_code
# -- Compiling architecture gold_code_arch of gold_code
VSIM 8> vsim -c gold_code
vsim -c gold_code
# vsim -c gold_code
# Loading c:\Modeltech_ae\win32aloem/../win32aloem/convert_hex2ver.dll
# Loading c:\Modeltech_ae\win32aloem/../std.standard
# Loading c:\Modeltech_ae\win32aloem/../ieee.std_logic_1164(body)
# Loading work.gold_code(gold_code_arch)
# Loading work.lfsr_a(lfsr_a_arch)
# Loading work.lfsr_b(lfsr_b_arch)
The code compiles and elaborates ok.
Note that the top entity is named gold_code, which does not match the
file name. For synthesis, all you need it to
enter the file list with vhd_top.vhd on top and push a button.
My problem is that the application note from xillinx does not work
properly at the test bench.
See page 9 of the pdf. There is no testbench unless you wrote one.
"The code was simulated on MTI's Modelsim simulator using the TCL
interface, therefore, no testbench was used. On a simulator supporting
stimulus using HDL code only, create the testbench (HDL) file to verify
functionality."
-- Mike Treseler
