handy_pack

[My Name]

This is a package that I've been adding to over time for my own use. I
know it could use some cleaning up here and there but I thought I'd post
it here for the use of anyone who's interested. If you have any useful
feedback on it feel free to respond to the email address in the file.

------------------------------------------------------------------------------
--
-- author : Michael Bills ([email protected])
--
-- description : This package has functions and procedures
-- for testbenching and assisting in RTL design
-- creation. It consists mostly of conversion functions.
-- some of them are mostly untested. Let me know if something
-- doesn't work
--
-- It uses functions from math_pack
-- so the use clauses for math_real and math_complex
-- may need to be modified based on the library
-- that they are compiled to.
--
------------------------------------------------------------------------------


-- LIBRARY STATEMENT
library ieee, handy_lib;

-- PACKAGE STATEMENT
use ieee.math_real.all;
use ieee.math_complex.all;
--use handy_lib.math_real.all;
--use handy_lib.math_complex.all;
use ieee.std_logic_1164.all;
--use ieee.std_logic_signed.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_arith.all;
use std.textio.all;


------------------------------------------------------------------------------
package handy_pack is
------------------------------------------------------------------------------


------------------------------------------------------------------------------
-- Type Declarations
------------------------------------------------------------------------------
type hexchar is ('0', '1', '2', '3', '4', '5', '6', '7',
'8', '9', 'A', 'B', 'C', 'D', 'E', 'F');

type hex is array (positive range <>) of hexchar;

type LED_Char is (' ', '"', ''', '-', '.', '/', '0', '1',
'2', '3', '4', '5', '6', '7', '8', '9',
'=', '?', 'A', 'B', 'C', 'D', 'E', 'F',
'G', 'H', 'I', 'J', 'K', 'L', 'O', 'P',
'S', 'T', 'U', 'Y', 'Z', '\', ']', '^',
'_', 'b', 'c', 'd', 'h', 'g', 'j', 'l',
'n', 'o', 'r', 'u', '¬', '­', '¯', '°',
'·');

type SevenSegLED is array (positive range <>) of LED_Char;


type frequency is range integer'low to integer'high
units
-- yoHz; -- yoctohertz 10E-24
-- zeHz = 1000 yoHz; -- zeptohertz 10E-21
-- aHz = 1000 zeHz; -- attohertz 10E-18
-- fHz = 1000 aHz; -- femtohertz 10E-15
-- piHz = 1000 fHz; -- picohertz 10E-12
-- nHz = 1000 piHz; -- nanohertz 10E-9
-- uHz = 1000 nHz; -- microhertz 10E-6
-- miHz = 1000 uHz; -- millihertz 10E-3
-- cHz = 10 miHz; -- centihertz 10E-2
-- dHz = 10 cHz; -- decihertz 10E-1
-- Hz = 10 dHz; -- hertz 10E0
Hz;
daHz = 10 Hz; -- dekahertz 10E+1
hHz = 10 daHz; -- hectohertz 10E+2
kHz = 10 hHz; -- kilohertz 10E+3
MHz = 1000 kHz; -- megahertz 10E+6
GHz = 1000 MHz; -- gigahertz 10E+9
THz = 1000 GHz; -- terahertz 10E+12 trillion 1/(1 fs)
PHz = 1000 THz; -- petahertz 10E+15 quadrillion
EHz = 1000 PHz; -- exahertz 10E+18 pentillion
ZHz = 1000 EHz; -- zettahertz 10E+21 sextillion
YHz = 1000 ZHz; -- yottahertz 10E+24 septillion
end units;
attribute frequency_resolution : real;
--attribute frequency_resolution of yohz : units is 0.000000000000000000000001;
--attribute frequency_resolution of zehz : units is 0.000000000000000000001;
--attribute frequency_resolution of ahz : units is 0.000000000000000001;
--attribute frequency_resolution of fhz : units is 0.000000000000001;
--attribute frequency_resolution of pihz : units is 0.000000000001;
--attribute frequency_resolution of nhz : units is 0.000000001;
--attribute frequency_resolution of uhz : units is 0.000001;
--attribute frequency_resolution of mihz : units is 0.001;
--attribute frequency_resolution of chz : units is 0.01;
--attribute frequency_resolution of dhz : units is 0.1;
attribute frequency_resolution of hz : units is 1.0;
attribute frequency_resolution of dahz : units is 10.0;
attribute frequency_resolution of hhz : units is 100.0;
attribute frequency_resolution of khz : units is 1000.0;
attribute frequency_resolution of Mhz : units is 1000000.0;
attribute frequency_resolution of Ghz : units is 1000000000.0;
attribute frequency_resolution of Thz : units is 1000000000000.0;
attribute frequency_resolution of Phz : units is 1000000000000000.0;
attribute frequency_resolution of Ehz : units is 1000000000000000000.0;
attribute frequency_resolution of Zhz : units is 1000000000000000000000.0;
attribute frequency_resolution of Yhz : units is 1000000000000000000000000.0;


--type real_time is range integer'low to integer'high
-- units
-- ys;
-- zs = 1000 ys;
-- as = 1000 zs;
-- fs = 1000 as;
-- ps = 1000 fs;
-- ns = 1000 ps;
-- us = 1000 ns;
-- ms = 1000 us;
-- cs = 10 ms;
-- ds = 10 cs;
-- sec = 10 ds;
-- min = 60 sec;
-- hr = 60 min;
-- end units;
--attribute time_resolution : real;
--attribute time_resolution of ys : units is 0.000000000000000000000001;
--attribute time_resolution of zs : units is 0.000000000000000000001;
--attribute time_resolution of as : units is 0.000000000000000001;
--attribute time_resolution of fs : units is 0.000000000000001;
--attribute time_resolution of ps : units is 0.000000000001;
--attribute time_resolution of ns : units is 0.000000001;
--attribute time_resolution of us : units is 0.000001;
--attribute time_resolution of ms : units is 0.001;
--attribute time_resolution of cs : units is 0.01;
--attribute time_resolution of ds : units is 0.1;
--attribute time_resolution of sec : units is 1.0;
--attribute time_resolution of min : units is 60.0;
--attribute time_resolution of hr : units is 3600.0;


------------------------------------------------------------------------------
-- Aliases
------------------------------------------------------------------------------
--alias bv is bit_vector;
--alias char is character;
--alias fok is file_open_kind;
--alias fos is file_open_status;
--alias int is integer;
--alias nat is natural;
--alias pos is positive;
--alias sl is std_logic;
--alias slv is std_logic_vector;
--alias str is string;
--alias sul is std_ulogic;
--alias sulv is std_ulogic_vector;
--alias uns is unsigned;


------------------------------------------------------------------------------
-- Subtype Declarations
------------------------------------------------------------------------------
subtype bv is bit_vector;
subtype char is character;
subtype fok is file_open_kind;
subtype fos is file_open_status;
subtype freq is frequency;
subtype int is integer;
subtype nat is natural;
subtype pos is positive;
subtype sl is std_logic;
subtype slv is std_logic_vector;
subtype str is string;
subtype sul is std_ulogic;
subtype sulv is std_ulogic_vector;
subtype uns is unsigned;


------------------------------------------------------------------------------
-- Constant Declarations
------------------------------------------------------------------------------


------------------------------------------------------------------------------
-- Function Declarations
------------------------------------------------------------------------------
function bcd_to_led(slvVal : std_logic_vector ;
CAVal : boolean) return std_logic_vector; -- binary coded decimal to seven segment LED conversion

function bcd_to_slv(vectorVal : std_logic_vector) return std_logic_vector; -- returns a packed BCD number in std_logic_vector form from the std_logic_vector passed to it using enough BCD digits to represent the largest value possible in the range of the vector passed

function bcd_to_slv_pipe(BCD_RVal : std_logic_vector;
BCD_DigitsVal : integer) return std_logic_vector; -- returns a packed BCD number in std_logic_vector form from the std_logic_vector passed to it using the number of BCD digits specified. For pipelined operation. function must be called N times where N is the number of bits in the passed value

function bv_to_slv(bitVectVal : bit_vector) return std_logic_vector; -- repackaging of "To_StdLogicVector" function

function conv_to_hex(vectorVal : bit_vector) return string; -- bit_vector to hexadecimal conversion
function conv_to_hex(vectorVal : std_logic_vector) return string; -- std_logic_vector to hexadecimal conversion
function conv_to_hex(vectorVal : std_ulogic_vector) return string; -- std_ulogic_vector to hexadecimal conversion

function cslv(int1Val : integer;
int2Val : integer) return std_logic_vector; -- repackaging of "conv_std_logic_vector"
function cslv(sigVal : signed;
intVal : integer) return std_logic_vector; -- repackaging of "conv_std_logic_vector"
function cslv(usgVal : unsigned;
intVal : integer) return std_logic_vector; -- repackaging of "conv_std_logic_vector"

function dpfi(intVal : integer) return natural; -- returns the number of decimal places for an integer value
function dpfr(realVal : real) return natural; -- returns the number of decimal places to the left of the decimal point for a real value

function dpfslvr(vectorVal : std_logic_vector) return natural; -- returns the number of decimal places needed to represent the full range of the std_logic_vector passed
function dpfslvv(vectorVal : std_logic_vector) return natural; -- returns the number of decimal places needed to represent the value of the std_logic_vector passed

function flip(vectorVal : bit_vector) return bit_vector; -- returns a bit_vector with all the bits in the reverse order
function flip(vectorVal : std_logic_vector) return std_logic_vector; -- returns a std_logic_vector with all the bits in the reverse order
function flip(vectorVal : std_ulogic_vector) return std_ulogic_vector; -- returns a std_ulogic_vector with all the bits in the reverse order

function int_to_slv(intVal : integer) return std_logic_vector; -- returns a std_logic_vector value just large enough to represent the integer value passed
function nat_to_slv(natVal : natural) return std_logic_vector; -- returns a std_logic_vector value just large enough to represent the natural value passed

function slv_to_bcd(vectorVal : std_logic_vector;
BCD_DigitsVal : integer) return std_logic_vector; -- returns a packed BCD number in std_logic_vector form from the std_logic_vector passed to it using the number of BCD digits specified
function slv_to_bcd(vectorVal : std_logic_vector) return std_logic_vector; -- returns a packed BCD number in std_logic_vector form from the std_logic_vector passed to it using enough BCD digits to represent the largest value possible in the range of the vector passed

function slv_to_bcd_pipe(BCD_RVal : std_logic_vector;
MSB_Val : std_logic;
BCD_DigitsVal : integer) return std_logic_vector; -- returns a packed BCD number in std_logic_vector form from the std_logic_vector passed to it using the number of BCD digits specified. For pipelined operation. function must be called N times where N is the number of bits in the passed value

function str_to_led(stringVal : string;
CAVal : boolean) return std_logic_vector; -- converts a Hexadecimal string of any length to a std_logic_vector for seven segment LEDs

function str_to_slv(stringVal : string) return std_logic_vector; -- converts a hexadeximal string to a standard logic vector

function time_to_slv(timeVal : time;
clkFreqVal : freq) return std_logic_vector;

function to_int(vectorVal : std_logic_vector) return integer; -- repackaging of "conv_integer" function

function to_period(freqVal : frequency) return time; -- returns a one cycle period value for a given frequency

function to_string(intVal : integer) return string; -- returns a string value for an integer value passed

function vhfi(intVal : integer) return natural; -- returns the high value to be used in the range declaration of a vector used to represent the integer value passed. This assumes the rest of the range declaration of the vector will be "downto 0"
function vhfn(natVal : natural) return natural; -- returns the high value to be used in the range declaration of a vector used to represent the natural value passed. This assumes the rest of the range declaration of the vector will be "downto 0"

function vlfi(intVal : integer) return natural; -- returns an integer representing the length of a vector needed to represent the integer value passed
function vlfn(natVal : natural) return natural; -- returns an integer representing the length of a vector needed to represent the natural value passed

function vrfi(intVal : integer) return std_logic_vector; -- returns a std_logic_vector with a range just large enough to represent the integer value passed


attribute int_vect : std_logic_vector;
attribute int_vect_range : natural;
--attribute int_vect of vrfi : function is vrfi;
--attribute int_vect_range of vrfi : function is vrfi'range;

function vrfn(natVal : natural) return std_logic_vector; -- returns a std_logic_vector with a range just large enough to represent the natural value passed


------------------------------------------------------------------------------
-- Procedure Declarations
------------------------------------------------------------------------------
procedure countdown_from(
signal timeVal : in time;
signal freqVal : in frequency;
signal enableIn : in std_logic;
signal count_RIn : in std_logic_vector;
signal count_Out : out std_logic_vector);

procedure FF(
signal Clk : in std_logic;
signal Rst : in std_logic;
signal D : in std_logic_vector;
signal Q : out std_logic_vector);

procedure slv_to_bcd(
signal BCD_RIn : in std_logic_vector;
signal BinIn : in std_logic_vector;
signal BinFBIn : in std_logic_vector;
signal ClkIn : in std_logic;
constant BCD_DigitsVal : in integer;
signal EnIn : in std_logic;
signal RstLowIn : in std_logic;
signal BCD_ROut : out std_logic_vector;
signal Bin_ROut : out std_logic_vector;
signal DoneOut : out std_logic);


------------------------------------------------------------------------------
end handy_pack;
------------------------------------------------------------------------------


------------------------------------------------------------------------------
package body handy_pack is
------------------------------------------------------------------------------





------------------------------------------------------------------------------
--
-- Functions
--
------------------------------------------------------------------------------


------------------------------------------------------------------------------
--
-- FUNCTION NAME : bcd_to_led
--
-- DESCRIPTION : This function converts a packed BCD vector into a seven
-- segment LED output
--
-- NOTES if the CAVal boolean input is true the output will
-- be for a Common Anode (1=off) display, otherwise it will
-- be for a Common Cathode (1=on)display.
-- _____
-- | a |
-- f| |b
-- |_____|
-- | g |
-- e| |c
-- |_____|
-- d
------------------------------------------------------------------------------
function bcd_to_led(slvVal : std_logic_vector ; CAVal : boolean) return std_logic_vector is
variable loopVar : integer;
variable resultVar : std_logic_vector(7*slvVal'length/4-1 downto 0);
variable vectorNormVar : std_logic_vector(slvVal'length-1 downto 0);
variable vectorParseVar : std_logic_vector(3 downto 0);
begin
vectorNormVar := slvVal;
for loopVar in 0 to slvVal'length/4-1 loop
vectorParseVar := vectorNormVar(4*loopVar+3 downto 4*loopVar);
case vectorParseVar is
-- Illuminated
-- vector Segment
-- value abcdefg
when "0000" => resultVar(7*loopVar+6 downto 7*loopvar) := "1111110"; -- 0
when "0001" => resultVar(7*loopVar+6 downto 7*loopvar) := "0110000"; -- 1
when "0010" => resultVar(7*loopVar+6 downto 7*loopvar) := "1101101"; -- 2
when "0011" => resultVar(7*loopVar+6 downto 7*loopvar) := "1111001"; -- 3
when "0100" => resultVar(7*loopVar+6 downto 7*loopvar) := "0110011"; -- 4
when "0101" => resultVar(7*loopVar+6 downto 7*loopvar) := "1011011"; -- 5
when "0110" => resultVar(7*loopVar+6 downto 7*loopvar) := "1011111"; -- 6
when "0111" => resultVar(7*loopVar+6 downto 7*loopvar) := "1110010"; -- 7
when "1000" => resultVar(7*loopVar+6 downto 7*loopvar) := "1111111"; -- 8
when "1001" => resultVar(7*loopVar+6 downto 7*loopvar) := "1110011"; -- 9
when others =>
end case;
end loop;
if (CAVal) then
return not resultVar;
else
return resultVar;
end if;
end bcd_to_led;


------------------------------------------------------------------------------
--
-- FUNCTION NAME : bcd_to_slv
--
-- DESCRIPTION : This function converts a packed binary coded decimal (BCD)
-- in standard logic vector for and returns an unsigned,
-- decending range, binary value
--
-- NOTES
--
------------------------------------------------------------------------------
function bcd_to_slv(vectorVal : std_logic_vector) return std_logic_vector is
type BCDArrayType is array(vectorVal'length downto 0) -- array depth is 1 level more than the input vector
of std_logic_vector(vectorVal'length-1 downto 0); --
variable CarryVar : std_logic_vector
(vectorVal'length/4 downto 0); -- the # of carry bits is determined by the number of BCD digits
variable BCD_WoCarVar : std_logic_vector(3 downto 0); -- BCD digit variable used by the inner loop if no carry to the next BCD Digit is needed
variable BCD_WiCarVar : std_logic_vector(3 downto 0); -- BCD digit variable used by the inner loop if carry to the next BCD Digit is needed
variable InnrLoopVar : integer := 0; -- inner loop index variable
variable OutrLoopVar : integer := 0; -- outer loop index variable
variable BCDVar : BCDArrayType; -- BCD value array
variable ResultVar : std_logic_vector(vectorVal'length-1 downto 0);
begin
BCDVar(0) := vectorVal; -- set the initial entry in the array to the input vector
for OutrLoopVar in 1 to vectorVal'length loop --
CarryVar(CarryVar'high) := '0';
for InnrLoopVar in CarryVar'high-1 downto 0 loop -- start at the MSB of the BCD vector
BCD_WoCarVar := '0' & BCDVar(OutrLoopVar-1) --
(4*InnrLoopVar+3 downto 4*InnrLoopVar+1); -- read the results of the previous calculation
BCD_WiCarVar := BCD_WoCarVar + "0101"; -- compute the result for the current BCD digit if carry is needed
CarryVar(InnrLoopVar) := BCDVar(OutrLoopVar-1)(4*InnrLoopVar); -- read in the next bit of the LSB of the previous BCD digit input into the lowest carry bit
if (CarryVar(InnrLoopVar+1) = '1') then -- if the the previous digit has a carry bit then then the result of the binary shift right is greater by 5
BCDVar(OutrLoopVar)
(4*InnrLoopVar+3 downto 4*InnrLoopVar) := BCD_WiCarVar;
else -- otherwise
BCDVar(OutrLoopVar)
(4*InnrLoopVar+3 downto 4*InnrLoopVar) := BCD_WoCarVar; -- we shift the bits right by 1 space
end if;
end loop;
ResultVar(OutrLoopVar-1) := BCDVar(OutrLoopVar-1)(0);
end loop;
return ResultVar;
end bcd_to_slv;


------------------------------------------------------------------------------
--
-- FUNCTION NAME : bcd_to_slv_pipe
--
-- DESCRIPTION : This function converts a packed binary coded decimal (BCD)
-- into an unsigned, decending range,
-- binary value into a standard logic vector and returns the result in
-- the number BCD digits required to represent the maximum
-- unsigned value possible in the vector passed to it.
-- it is for use in pipelined implementations where
-- the binary coded decimal output is registered
-- and passed back to the function along with the binary
-- vector input to be shifted out of its MSB
-- register and into the function as a new bit.
--
--
-- NOTES
-- BCD_DigitsVal -> dpfslvr(vectorVal)
------------------------------------------------------------------------------
function bcd_to_slv_pipe(
BCD_RVal : std_logic_vector; -- registered output of this function fed back in
BCD_DigitsVal : integer) return std_logic_vector is -- binary coded decimal arithmetic shift right
variable CarryVar : std_logic_vector(BCD_DigitsVal downto 0) := (others => '0'); -- the # of carry bits is determined by the number of BCD digits
variable BCD_WoCarVar : std_logic_vector(3 downto 0);
variable BCD_WiCarVar : std_logic_vector(3 downto 0);
variable ResultVar : std_logic_vector(4*BCD_DigitsVal-1 downto 0);
begin
CarryVar(CarryVar'high) := '0';
for loopVar in BCD_DigitsVal-1 downto 0 loop
BCD_WoCarVar := '0' & BCD_RVal(4*loopVar+3 downto 4*loopVar+1);
BCD_WiCarVar := BCD_WoCarVar + "0101";
CarryVar(loopVar) := BCD_RVal(4*loopVar);
if (CarryVar(loopVar+1) = '1') then
ResultVar(4*loopVar+3 downto 4*loopVar) := BCD_WiCarVar;
else
ResultVar(4*loopVar+3 downto 4*loopVar) := BCD_WoCarVar;
end if;
end loop;
return ResultVar;
end bcd_to_slv_pipe;


------------------------------------------------------------------------------
--
-- FUNCTION NAME : bv_to_slv (convert integer to std_logic_vector)
--
-- DESCRIPTION : This function converts an integer (int1Val)
-- to a std logic vector of length int2Val.
--
-- NOTES
--
------------------------------------------------------------------------------
function bv_to_slv(bitVectVal : bit_vector) return std_logic_vector is
begin
return To_StdLogicVector(bitVectVal);
end bv_to_slv;


------------------------------------------------------------------------------
--
-- FUNCTION NAME : conv_to_hex
--
-- DESCRIPTION : This function converts a bit vector of any length to a
-- string representing the Hexadecimal value of that vector
-- NOTES
--
------------------------------------------------------------------------------
function conv_to_hex(vectorVal : bit_vector) return string is
variable loopVar : integer;
variable resultVar : string(integer(ceil(real(vectorVal'length)/4.0)) downto 1);
variable vectorParseVar : std_logic_vector(4 downto 1);
variable vectorStretchVar : std_logic_vector((integer(ceil(real(vectorVal'length)/4.0)))*4 downto 1);
begin
vectorStretchVar := ext(to_stdlogicvector(vectorVal),vectorStretchVar'length);
for loopVar in resultVar'range loop
vectorParseVar := vectorStretchVar(loopVar*4 downto loopVar*4-4);
case vectorParseVar(4 downto 1) is
when "0000" => resultVar(loopVar) := '0';
when "0001" => resultVar(loopVar) := '1';
when "0010" => resultVar(loopVar) := '2';
when "0011" => resultVar(loopVar) := '3';
when "0100" => resultVar(loopVar) := '4';
when "0101" => resultVar(loopVar) := '5';
when "0110" => resultVar(loopVar) := '6';
when "0111" => resultVar(loopVar) := '7';
when "1000" => resultVar(loopVar) := '8';
when "1001" => resultVar(loopVar) := '9';
when "1010" => resultVar(loopVar) := 'A';
when "1011" => resultVar(loopVar) := 'B';
when "1100" => resultVar(loopVar) := 'C';
when "1101" => resultVar(loopVar) := 'D';
when "1110" => resultVar(loopVar) := 'E';
when "1111" => resultVar(loopVar) := 'F';
when others =>
end case;
end loop;
return resultVar;
end conv_to_hex;


------------------------------------------------------------------------------
--
-- FUNCTION NAME : conv_to_hex
--
-- DESCRIPTION : This function converts a logic vector of any length to a
-- string representing the Hexadecimal value of that vector
-- NOTES
--
------------------------------------------------------------------------------
function conv_to_hex(vectorVal : std_logic_vector) return string is
variable loopVar : integer;
variable resultVar : string(integer(ceil(real(vectorVal'length)/4.0)) downto 1);
variable vectorParseVar : std_logic_vector(4 downto 1);
variable vectorStretchVar : std_logic_vector((integer(ceil(real(vectorVal'length)/4.0)))*4 downto 1);
begin
vectorStretchVar := ext(vectorVal,vectorStretchVar'length);
for loopVar in resultVar'range loop
vectorParseVar := vectorStretchVar(loopVar*4 downto loopVar*4-4);
case vectorParseVar(4 downto 1) is
when "0000" => resultVar(loopVar) := '0';
when "0001" => resultVar(loopVar) := '1';
when "0010" => resultVar(loopVar) := '2';
when "0011" => resultVar(loopVar) := '3';
when "0100" => resultVar(loopVar) := '4';
when "0101" => resultVar(loopVar) := '5';
when "0110" => resultVar(loopVar) := '6';
when "0111" => resultVar(loopVar) := '7';
when "1000" => resultVar(loopVar) := '8';
when "1001" => resultVar(loopVar) := '9';
when "1010" => resultVar(loopVar) := 'A';
when "1011" => resultVar(loopVar) := 'B';
when "1100" => resultVar(loopVar) := 'C';
when "1101" => resultVar(loopVar) := 'D';
when "1110" => resultVar(loopVar) := 'E';
when "1111" => resultVar(loopVar) := 'F';
when others =>
end case;
end loop;
return resultVar;
end conv_to_hex;


------------------------------------------------------------------------------
--
-- FUNCTION NAME : conv_to_hex
--
-- DESCRIPTION : This function converts a ulogic vector of any length to a
-- string representing the Hexadecimal value of that vector
-- NOTES
--
------------------------------------------------------------------------------
function conv_to_hex(vectorVal : std_ulogic_vector) return string is
variable loopVar : integer;
variable resultVar : string(integer(ceil(real(vectorVal'length)/4.0)) downto 1);
variable vectorParseVar : std_logic_vector(4 downto 1);
variable vectorStretchVar : std_logic_vector((integer(ceil(real(vectorVal'length)/4.0)))*4 downto 1);
begin
vectorStretchVar := ext(to_stdlogicvector(vectorVal),vectorStretchVar'length);
for loopVar in resultVar'range loop
vectorParseVar := vectorStretchVar(loopVar*4 downto loopVar*4-4);
case vectorParseVar(4 downto 1) is
when "0000" => resultVar(loopVar) := '0';
when "0001" => resultVar(loopVar) := '1';
when "0010" => resultVar(loopVar) := '2';
when "0011" => resultVar(loopVar) := '3';
when "0100" => resultVar(loopVar) := '4';
when "0101" => resultVar(loopVar) := '5';
when "0110" => resultVar(loopVar) := '6';
when "0111" => resultVar(loopVar) := '7';
when "1000" => resultVar(loopVar) := '8';
when "1001" => resultVar(loopVar) := '9';
when "1010" => resultVar(loopVar) := 'A';
when "1011" => resultVar(loopVar) := 'B';
when "1100" => resultVar(loopVar) := 'C';
when "1101" => resultVar(loopVar) := 'D';
when "1110" => resultVar(loopVar) := 'E';
when "1111" => resultVar(loopVar) := 'F';
when others =>
end case;
end loop;
return resultVar;
end conv_to_hex;


------------------------------------------------------------------------------
--
-- FUNCTION NAME : cslv (convert integer to std_logic_vector)
--
-- DESCRIPTION : This function converts an integer (int1Val)
-- to a std logic vector of length int2Val.
--
-- NOTES
--
------------------------------------------------------------------------------
function cslv(int1Val : integer; int2Val : integer) return std_logic_vector is
begin
return conv_std_logic_vector(int1Val,int2Val);
end cslv;


------------------------------------------------------------------------------
--
-- FUNCTION NAME : cslv (convert signed to std_logic_vector)
--
-- DESCRIPTION : This function converts an signed value
-- to a std logic vector of length intVal.
--
-- NOTES
--
------------------------------------------------------------------------------
function cslv(sigVal : signed; intVal : integer) return std_logic_vector is
begin
return conv_std_logic_vector(sigVal,intVal);
end cslv;


------------------------------------------------------------------------------
--
-- FUNCTION NAME : cslv (convert integer to std_logic_vector)
--
-- DESCRIPTION : This function converts an unsigned value
-- to a std logic vector of length intVal.
--
-- NOTES
--
------------------------------------------------------------------------------
function cslv(usgVal : unsigned; intVal : integer) return std_logic_vector is
begin
return conv_std_logic_vector(usgVal,intVal);
end cslv;


------------------------------------------------------------------------------
--
-- FUNCTION NAME : dpfi (decimal places for integer)
--
-- DESCRIPTION : This function returns a natural representing the
-- number of digits in an integer value. It is essentially
-- an integer'length function.
--
-- NOTES :
--
------------------------------------------------------------------------------
function dpfi(intVal : integer) return natural is
variable PowerOfTenVar : integer := 10;
variable CountVar : natural := 1;
begin
while true loop
if (intVal < PowerOfTenVar) then -- if the value is less than the current power of ten then
exit; -- exit the loop (and return the current power of ten)
else -- otherwise
CountVar := CountVar + 1; -- increment the decimal counter
if ((real(integer'high)/real(PowerOfTenVar)) < 10.0) then -- and if we are within a power of ten of the integer range then
exit; -- exit the loop (and return the new count value)
else -- otherwise
PowerOfTenVar := PowerOfTenVar * 10; -- increase the comparison value by a power of ten
end if;
end if;
end loop;
return CountVar;
end dpfi;


-- synthesizable version
--function dpfi(intVal : integer) return natural is
-- variable resultVar : natural;
--begin
-- if (intVal <= -1_000_000_000 or intVal >= 1_000_000_000) then
-- resultVar := 10;
-- elsif (intVal <= -100_000_000 or intVal >= 100_000_000) then
-- resultVar := 9;
-- elsif (intVal <= -10_000_000 or intVal >= 10_000_000) then
-- resultVar := 8;
-- elsif (intVal <= -1_000_000 or intVal >= 1_000_000) then
-- resultVar := 7;
-- elsif (intVal <= -100_000 or intVal >= 100_000) then
-- resultVar := 6;
-- elsif (intVal <= -10_000 or intVal >= 10_000) then
-- resultVar := 5;
-- elsif (intVal <= -1_000 or intVal >= 1_000) then
-- resultVar := 4;
-- elsif (intVal <= -100 or intVal >= 100) then
-- resultVar := 3;
-- elsif (intVal <= -10 or intVal >= 10) then
-- resultVar := 2;
-- else
-- resultVar := 1;
-- end if;
-- return resultVar;
--end dpfi;


------------------------------------------------------------------------------
--
-- FUNCTION NAME : dpfr (decimal places for real)
--
-- DESCRIPTION : This function returns an natural representing the
-- number of digits to the left of the decimal
-- in an real value.
--
-- NOTES :
--
------------------------------------------------------------------------------
function dpfr(realVal : real) return natural is
variable PowerOfTenVar : real := 10.0;
variable CountVar : natural := 1;
begin
while true loop
if (realVal < PowerOfTenVar) then -- if the value is less than the current power of ten then
exit; -- exit the loop (and return the current power of ten)
else -- otherwise
CountVar := CountVar + 1; -- increment the decimal counter
if ((real'high/PowerOfTenVar) < 10.0) then -- and if we are within a power of ten of the integer range then
exit; -- exit the loop (and return the new count value)
else -- otherwise
PowerOfTenVar := PowerOfTenVar * 10.0; -- increase the comparison value by a power of ten
end if;
end if;
end loop;
return CountVar;
end dpfr;


------------------------------------------------------------------------------
--
-- FUNCTION NAME : dpfslvr (decimal places for slv range)
--
-- DESCRIPTION : This function returns a natural representing the
-- number of decimal places the largest integer value that
-- can be represented by a vector will occupy.
--
-- NOTES :
--
------------------------------------------------------------------------------
function dpfslvr(vectorVal : std_logic_vector) return natural is
variable returnVar : std_logic_vector(vectorVal'length-1 downto 0) := (others => '1');
begin
return dpfi(conv_integer(returnVar));
end dpfslvr;


------------------------------------------------------------------------------
--
-- FUNCTION NAME : dpfslvv (decimal places for slv value)
--
-- DESCRIPTION : This function returns a natural representing the
-- number of decimal places the integer value represented
-- by a vector will occupy.
--
-- NOTES :
--
------------------------------------------------------------------------------
function dpfslvv(vectorVal : std_logic_vector) return natural is
begin
return dpfi(conv_integer(vectorVal));
end dpfslvv;


------------------------------------------------------------------------------
--
-- FUNCTION NAME : flip
--
-- DESCRIPTION : This function returns a vector with all the bits
-- in the vector flipped.
-- i.e. if vectorval = 00011001
-- flip(vectorval) returns 10011000
-- NOTES
--
------------------------------------------------------------------------------
function flip(vectorVal : bit_vector) return bit_vector is
variable loopVar : integer;
variable resultVar : bit_vector(vectorVal'range);
begin
for loopVar in vectorVal'range loop
resultVar(resultVar'high-loopVar) := vectorVal(loopVar);
end loop;
return resultVar;
end flip;


------------------------------------------------------------------------------
--
-- FUNCTION NAME : flip
--
-- DESCRIPTION : This function returns a vector with all the bits
-- in the vector flipped.
-- i.e. if vectorval = 00011001
-- flip(vectorval) returns 10011000
-- NOTES
--
------------------------------------------------------------------------------
function flip(vectorVal : std_logic_vector) return std_logic_vector is
variable loopVar : integer;
variable resultVar : std_logic_vector(vectorVal'range);
begin
for loopVar in vectorVal'range loop
resultVar(resultVar'high-loopVar) := vectorVal(loopVar);
end loop;
return resultVar;
end flip;


------------------------------------------------------------------------------
--
-- FUNCTION NAME : flip
--
-- DESCRIPTION : This function returns a vector with all the bits
-- in the vector flipped.
-- i.e. if vectorval = 00011001
-- flip(vectorval) returns 10011000
-- NOTES
--
------------------------------------------------------------------------------
function flip(vectorVal : std_ulogic_vector) return std_ulogic_vector is
variable loopVar : integer;
variable resultVar : std_ulogic_vector(vectorVal'range);
begin
for loopVar in vectorVal'range loop
resultVar(resultVar'high-loopVar) := vectorVal(loopVar);
end loop;
return resultVar;
end flip;


------------------------------------------------------------------------------
--
-- FUNCTION NAME : int_to_slv (convert integer to std_logic_vector)
--
-- DESCRIPTION : This function converts an integer value to a
-- std_logic_vector with a range just large enough
-- to represent it
--
-- NOTES
--
------------------------------------------------------------------------------
function int_to_slv(intVal : integer) return std_logic_vector is
begin
return conv_std_logic_vector(intVal,vlfi(intVal));
end int_to_slv;


------------------------------------------------------------------------------
--
-- FUNCTION NAME : nat_to_slv (convert natural to std_logic_vector)
--
-- DESCRIPTION : This function converts a natural value to a
-- std_logic_vector with a range just large enough
-- to represent it
--
-- NOTES
--
------------------------------------------------------------------------------
function nat_to_slv(natVal : natural) return std_logic_vector is
begin
return conv_std_logic_vector(natVal,vlfn(natVal));
end nat_to_slv;


------------------------------------------------------------------------------
--
-- FUNCTION NAME : slv_to_bcd
--
-- DESCRIPTION : This function converts an unsigned, decending range,
-- std logic vector value into a
-- packed binary coded decimal (BCD)
-- standard logic vector and returns the result in
-- the number of BCD digits passed to the function.
--
-- NOTES
--
------------------------------------------------------------------------------
function slv_to_bcd(vectorVal : std_logic_vector; BCD_DigitsVal : integer)
return std_logic_vector is
type resultArrayType is array(vectorVal'length downto 0) -- array depth is 1 level more than the input vector
of std_logic_vector(4*BCD_DigitsVal-1 downto 0); -- array width is determined by the number of BCD digits to output
variable CarryVar : std_logic_vector(BCD_DigitsVal downto 0); -- the # of carry bits is determined by the number of BCD digits
variable BCD_WoCarVar : std_logic_vector(3 downto 0); -- BCD digit variable used by the inner loop if the next BCD Digit is computed without carry from the current BCD value
variable BCD_WiCarVar : std_logic_vector(3 downto 0); -- BCD digit variable used by the inner loop if the next BCD Digit is computed with carry from the current BCD value
variable InnrLoopVar : integer := 0; -- inner loop index variable
variable OutrLoopVar : integer := 0; -- outer loop index variable
variable ResultVar : resultArrayType; -- BCD value result variable
begin
ResultVar(0) := (others => '0'); -- set the initial entry in the results array to zero
for OutrLoopVar in vectorVal'high downto 0 loop -- start at the MSB of the std logic vector input and work down
CarryVar(0) := vectorVal(OutrLoopVar); -- read in the next bit of the slv input into the lowest carry bit
for InnrLoopVar in 0 to BCD_DigitsVal-1 loop -- start at the LSB of the BCD output
BCD_WoCarVar := ResultVar(vectorVal'length - OutrLoopVar -1) -- read the results of the previous calculation
(4*InnrLoopVar+3 downto 4*InnrLoopVar);
BCD_WiCarVar := BCD_WoCarVar - "0101"; -- compute the result for the current BCD digit if a carry to the next digit will be needed
if (BCD_WoCarVar > "0100") then -- if the digit is 5 or greater ("0101") then the result of the binary shift left "10100" = decimal 16, which is to great to represent in one BCD digit so then
CarryVar(InnrLoopVar+1) := '1'; -- we carry a digit to the next BCD digit
ResultVar(vectorVal'length - OutrLoopVar)
(4*InnrLoopVar+3 downto 4*InnrLoopVar)
:= BCD_WiCarVar(2 downto 0) & CarryVar(InnrLoopVar); -- and we use the lesser value for the current digit along with the carry value from the previous BCD digit
else -- otherwise the digit is small enough to be represented in one BCD digit when a binary shift in is performed
CarryVar(InnrLoopVar+1) := '0';
ResultVar(vectorVal'length - OutrLoopVar)
(4*InnrLoopVar+3 downto 4*InnrLoopVar)
:= BCD_WoCarVar(2 downto 0) & CarryVar(InnrLoopVar); -- so we write the value to the result variable along with any carry value from a previous BCD digit
end if;
end loop;
end loop;
return ResultVar(vectorVal'high+1);
end slv_to_bcd;


------------------------------------------------------------------------------
--
-- FUNCTION NAME : slv_to_bcd
--
-- DESCRIPTION : This function converts an unsigned, decending range,
-- binary value into a packed binary coded decimal (BCD)
-- standard logic vector and returns the result in
-- the number BCD digits required to represent the maximum
-- unsigned value possible in the vector passed to it
--
-- NOTES
-- BCD_DigitsVal -> dpfslvr(vectorVal)
------------------------------------------------------------------------------
function slv_to_bcd(vectorVal : std_logic_vector) return std_logic_vector is
type resultArrayType is array(vectorVal'length downto 0) -- array depth is 1 level more than the input vector
of std_logic_vector(4*dpfslvr(vectorVal)-1 downto 0); -- array width is determined by the number of BCD digits to output
variable CarryVar : std_logic_vector
(dpfslvr(vectorVal) downto 0); -- the # of carry bits is determined by the number of BCD digits
variable BCD_WoCarVar : std_logic_vector(3 downto 0); -- BCD digit variable used by the inner loop if no carry to the next BCD Digit is needed
variable BCD_WiCarVar : std_logic_vector(3 downto 0); -- BCD digit variable used by the inner loop if carry to the next BCD Digit is needed
variable InnrLoopVar : integer := 0; -- inner loop index variable
variable OutrLoopVar : integer := 0; -- outer loop index variable
variable ResultVar : resultArrayType; -- BCD value result variable
begin
ResultVar(0) := (others => '0'); -- set the initial entry in the results array to zero
for OutrLoopVar in vectorVal'high downto 0 loop -- start at the MSB of the std logic vector input and work down
CarryVar(0) := vectorVal(OutrLoopVar); -- read in the next bit of the slv input into the lowest carry bit
for InnrLoopVar in 0 to CarryVar'high-1 loop -- start at the LSB of the BCD output
BCD_WoCarVar := ResultVar(vectorVal'length - OutrLoopVar -1) -- read the results of the previous calculation
(4*InnrLoopVar+3 downto 4*InnrLoopVar);
BCD_WiCarVar := BCD_WoCarVar - "0101"; -- compute the result for the current BCD digit if a carry to the next digit will be needed
if (BCD_WoCarVar > "0100") then -- if the digit is 5 or greater ("0101") then the result of the binary shift left "10100" = decimal 16, which is to great to represent in one BCD digit so then
CarryVar(InnrLoopVar+1) := '1'; -- we carry a digit to the next BCD digit
ResultVar(vectorVal'length - OutrLoopVar)
(4*InnrLoopVar+3 downto 4*InnrLoopVar)
:= BCD_WiCarVar(2 downto 0) & CarryVar(InnrLoopVar); -- and we use the lesser value for the current digit along with the carry value from the previous BCD digit
else -- otherwise the digit is small enough to be represented in one BCD digit when a binary shift in is performed
CarryVar(InnrLoopVar+1) := '0';
ResultVar(vectorVal'length - OutrLoopVar)
(4*InnrLoopVar+3 downto 4*InnrLoopVar)
:= BCD_WoCarVar(2 downto 0) & CarryVar(InnrLoopVar); -- so we write the value to the result variable along with any carry value from a previous BCD digit
end if;
end loop;
end loop;
return ResultVar(vectorVal'high+1);
end slv_to_bcd;


------------------------------------------------------------------------------
--
-- FUNCTION NAME : slv_to_bcd_pipe
--
-- DESCRIPTION : This function converts an unsigned, decending range,
-- binary value into a packed binary coded decimal (BCD)
-- standard logic vector and returns the result in
-- the number BCD digits required to represent the maximum
-- unsigned value possible in the vector passed to it.
-- it is for use in pipelined implementations where
-- the binary coded decimal output is registered
-- and passed back to the function along with the binary
-- vector input to be shifted out of its MSB
-- register and into the function as a new bit.
--
--
-- NOTES
-- BCD_DigitsVal -> dpfslvr(vectorVal)
------------------------------------------------------------------------------
function slv_to_bcd_pipe(
BCD_RVal : std_logic_vector; -- registered output of this function fed back in
MSB_Val : std_logic; -- msb of binary value being shifted in
BCD_DigitsVal : integer) return std_logic_vector is -- binary coded decimal arithmetic shift left
variable CarryVar : std_logic_vector(BCD_DigitsVal downto 0); -- the # of carry bits is determined by the number of BCD digits
variable BCD_WoCarVar : std_logic_vector(3 downto 0);
variable BCD_WiCarVar : std_logic_vector(3 downto 0);
variable ResultVar : std_logic_vector(4*BCD_DigitsVal-1 downto 0);
begin
for loopVar in 0 to BCD_DigitsVal-1 loop
CarryVar(0) := MSB_Val;
BCD_WoCarVar := BCD_RVal(4*loopVar+3 downto 4*loopVar);
BCD_WiCarVar := BCD_WoCarVar - "0101";
if (BCD_WoCarVar > "0100") then
CarryVar(loopVar+1) := '1';
ResultVar(4*loopVar+3 downto 4*loopVar)
:= BCD_WiCarVar(2 downto 0) & CarryVar(loopVar);
else
CarryVar(loopVar+1) := '0';
ResultVar(4*loopVar+3 downto 4*loopVar)
:= BCD_WoCarVar(2 downto 0) & CarryVar(loopVar);
end if;
end loop;
return ResultVar;
end slv_to_bcd_pipe;


------------------------------------------------------------------------------
--
-- FUNCTION NAME : str_to_led
--
-- DESCRIPTION : This function converst a Seven Segment LED
-- string of any length to a std_logic_vector
--
-- NOTES : if the CAVal boolean input is true the output will
-- be for a Common Anode (1=off) display, otherwise it will
-- be for a Common Cathode (1=on)display.
--
-- _____
-- | a |
-- f| |b
-- |_____|
-- | g |
-- e| |c
-- |_____|
-- d
--
------------------------------------------------------------------------------
function str_to_led(stringVal : string;
CAVal : boolean) return std_logic_vector is
variable loopVar : integer;
variable resultVar : std_logic_vector(7*StringVal'length downto 1);
variable vectorParseVar : character;
begin

for loopVar in StringVal'range loop
vectorParseVar := StringVal(loopVar);
case vectorParseVar is
-- Illuminated
-- character Segment
-- shown abcdefg
when ' ' => resultVar(7*loopVar downto 7*loopVar-6) := "0000000";
when '"' => resultVar(7*loopVar downto 7*loopVar-6) := "0100010";
when ''' => resultVar(7*loopVar downto 7*loopVar-6) := "0100000";
when '-' => resultVar(7*loopVar downto 7*loopVar-6) := "0000001";
when '/' => resultVar(7*loopVar downto 7*loopVar-6) := "0100101";
when '0' | 'D' => resultVar(7*loopVar downto 7*loopVar-6) := "1111110";
when '1' => resultVar(7*loopVar downto 7*loopVar-6) := "0110000";
when '2' => resultVar(7*loopVar downto 7*loopVar-6) := "1101101";
when '3' => resultVar(7*loopVar downto 7*loopVar-6) := "1111001";
when '4' => resultVar(7*loopVar downto 7*loopVar-6) := "0110011";
when '5' | 'S' => resultVar(7*loopVar downto 7*loopVar-6) := "1011011";
when '6' => resultVar(7*loopVar downto 7*loopVar-6) := "1011111";
when '7' => resultVar(7*loopVar downto 7*loopVar-6) := "1110010";
when '8' | 'B' => resultVar(7*loopVar downto 7*loopVar-6) := "1111111";
when '9' => resultVar(7*loopVar downto 7*loopVar-6) := "1110011";
when '=' => resultVar(7*loopVar downto 7*loopVar-6) := "0001001";
when '?' => resultVar(7*loopVar downto 7*loopVar-6) := "1100101";
when 'A' => resultVar(7*loopVar downto 7*loopVar-6) := "1110111";
when 'C' => resultVar(7*loopVar downto 7*loopVar-6) := "1001110";
when 'E' => resultVar(7*loopVar downto 7*loopVar-6) := "1001111";
when 'F' => resultVar(7*loopVar downto 7*loopVar-6) := "1000111";
when 'G' => resultVar(7*loopVar downto 7*loopVar-6) := "1011110";
when 'H' => resultVar(7*loopVar downto 7*loopVar-6) := "0110111";
when 'I' => resultVar(7*loopVar downto 7*loopVar-6) := "0000110";
when 'J' => resultVar(7*loopVar downto 7*loopVar-6) := "1111100";
when 'L' => resultVar(7*loopVar downto 7*loopVar-6) := "0001110";
when 'O' => resultVar(7*loopVar downto 7*loopVar-6) := "1111110";
when 'P' => resultVar(7*loopVar downto 7*loopVar-6) := "1100111";
when 'T' => resultVar(7*loopVar downto 7*loopVar-6) := "1000110";
when 'U' => resultVar(7*loopVar downto 7*loopVar-6) := "0111110";
when 'Y' => resultVar(7*loopVar downto 7*loopVar-6) := "0100111";
when 'Z' => resultVar(7*loopVar downto 7*loopVar-6) := "1101101";
when '\' => resultVar(7*loopVar downto 7*loopVar-6) := "0010011";
when ']' => resultVar(7*loopVar downto 7*loopVar-6) := "1111000";
when '^' => resultVar(7*loopVar downto 7*loopVar-6) := "1100010";
when '_' => resultVar(7*loopVar downto 7*loopVar-6) := "0001000";
when 'b' => resultVar(7*loopVar downto 7*loopVar-6) := "0011111";
when 'c' => resultVar(7*loopVar downto 7*loopVar-6) := "0001101";
when 'd' => resultVar(7*loopVar downto 7*loopVar-6) := "0111101";
when 'g' => resultVar(7*loopVar downto 7*loopVar-6) := "1111011";
when 'h' => resultVar(7*loopVar downto 7*loopVar-6) := "0010111";
when 'j' => resultVar(7*loopVar downto 7*loopVar-6) := "0111100";
when 'l' => resultVar(7*loopVar downto 7*loopVar-6) := "0111000";
when 'n' => resultVar(7*loopVar downto 7*loopVar-6) := "0010101";
when 'o' => resultVar(7*loopVar downto 7*loopVar-6) := "0011101";
when 'r' => resultVar(7*loopVar downto 7*loopVar-6) := "0000101";
when 'u' => resultVar(7*loopVar downto 7*loopVar-6) := "0011100";
when '¬' => resultVar(7*loopVar downto 7*loopVar-6) := "0010001";
when '¯' => resultVar(7*loopVar downto 7*loopVar-6) := "1000000";
when '°' => resultVar(7*loopVar downto 7*loopVar-6) := "1100011";
when others =>
end case;
end loop;
if (CAVal) then
return not resultVar;
else
return resultVar;
end if;
end str_to_led;


------------------------------------------------------------------------------
--
-- FUNCTION NAME : str_to_slv
--
-- DESCRIPTION : This function converts a Hexadecimal string
-- of any length to a std_logic_vector
--
-- NOTES
--
------------------------------------------------------------------------------
function str_to_slv(stringVal : string) return std_logic_vector is
variable loopVar : integer;
variable resultVar : std_logic_vector(4*stringVal'length downto 1);
variable vectorParseVar : character;
begin
for loopVar in stringVal'range loop
vectorParseVar := stringVal(loopVar);
case vectorParseVar is
when '0' => resultVar(4*loopVar downto 4*loopvar-3) := "0000";
when '1' => resultVar(4*loopVar downto 4*loopvar-3) := "0001";
when '2' => resultVar(4*loopVar downto 4*loopvar-3) := "0010";
when '3' => resultVar(4*loopVar downto 4*loopvar-3) := "0011";
when '4' => resultVar(4*loopVar downto 4*loopvar-3) := "0100";
when '5' => resultVar(4*loopVar downto 4*loopvar-3) := "0101";
when '6' => resultVar(4*loopVar downto 4*loopvar-3) := "0110";
when '7' => resultVar(4*loopVar downto 4*loopvar-3) := "0111";
when '8' => resultVar(4*loopVar downto 4*loopvar-3) := "1000";
when '9' => resultVar(4*loopVar downto 4*loopvar-3) := "1001";
when 'a' | 'A' => resultVar(4*loopVar downto 4*loopvar-3) := "1010";
when 'b' | 'B' => resultVar(4*loopVar downto 4*loopvar-3) := "1011";
when 'c' | 'C' => resultVar(4*loopVar downto 4*loopvar-3) := "1100";
when 'd' | 'D' => resultVar(4*loopVar downto 4*loopvar-3) := "1101";
when 'e' | 'E' => resultVar(4*loopVar downto 4*loopvar-3) := "1110";
when 'f' | 'F' => resultVar(4*loopVar downto 4*loopvar-3) := "1111";
when others =>
end case;
end loop;
return resultVar;
end str_to_slv;


------------------------------------------------------------------------------
--
-- FUNCTION NAME : time_to_slv (convert time to slv)
--
-- DESCRIPTION : converts a time value referenced to a clock frequency
-- to a standard logic vector value large enough to
-- represent it as a signed integer value
--
-- NOTES
--
------------------------------------------------------------------------------
function time_to_slv(timeVal : time;
clkFreqVal : freq) return std_logic_vector is
variable resultVar : std_logic_vector(int_to_slv(timeVal/to_period(clkFreqVal))'range);
begin
resultVar := int_to_slv(timeVal/to_period(clkFreqVal));
return resultVar;
end time_to_slv;


------------------------------------------------------------------------------
--
-- FUNCTION NAME : to_int
--
-- DESCRIPTION : conv_integer function repackaged
--
-- NOTES
--
------------------------------------------------------------------------------
function to_int(vectorVal : std_logic_vector) return integer is
begin
return conv_integer(vectorVal);
end to_int;


------------------------------------------------------------------------------
--
-- FUNCTION NAME : to_period
--
-- DESCRIPTION : This function returns a one cycle period value for
-- a given frequency
--
-- NOTES timeVar must be larger than the simulator resolution
-- and is limited by the integer that can be created from
-- time'pos of it's value
------------------------------------------------------------------------------
function to_period(freqVal : frequency) return time is
variable resultVar : time;
variable timeVar : time := 1 ms;
variable divVar : real := real(1 sec/timeVar);
begin
if (freq'pos(freqVal) > integer'high) then
assert FALSE
report "Frequency value passed to function greater than integer'high when converted to base units."
severity warning;
end if;
resultVar := real(divVar/real(freq'pos(freqVal))) * timeVar; -- see "NOTES"
return resultVar;
end to_period;


------------------------------------------------------------------------------
--
-- FUNCTION NAME : to_string
--
-- DESCRIPTION : This function returns a string value representing the
-- value passed to it.
-- NOTES
--
------------------------------------------------------------------------------
-- synopsys translate_off
function to_string(intVal : integer) return string is
variable lineVar : line;
variable resultVar : string(1 to dpfi(intVal));
begin
--Std.TextIO.Write(lineVar, intVal);
Write(lineVar, intVal);
--resultVar(lineVar.all'range) := lineVar.all;
resultVar := lineVar.all;
deallocate(lineVar);
return resultVar;
end to_string;
-- synopsys translate_on


--------------------------------------------------------------------------------
----
---- PROCEDURE NAME : transpose
----
---- DESCRIPTION : This procedure returns the transpose of an array
----
---- NOTES : column 1 -> row 1
---- column 2 -> row 2
----
--------------------------------------------------------------------------------
--procedure( transpose(arrayVal : array_type) return array_type is
-- variable loopVar : natural;
-- variable resultVar : std_ulogic_vector(vectorVal'range);
--begin
-- for loopVar in vectorVal'low to vectorVal'high loop
-- resultVar(resultVar'high-loopVar) := vectorVal(loopVar);
-- end loop;
-- return resultVar;
--end transpose;


------------------------------------------------------------------------------
--
-- FUNCTION NAME : vhfi (vector high for integer)
--
-- DESCRIPTION : This function returns the 'high value to be used
-- in the range declaration of a vector used to
-- represent the integer value passed to it.
--
-- WARNING: This function assumes the rest of the
-- range declaration of the vector
-- will be "downto 0"
--
-- NOTES : see vlfi for more information
--
-- EXAMPLE :
------------------------------------------------------------------------------
function vhfi(intVal : integer) return natural is
begin
return vlfi(intVal) - 1;
end vhfi;


------------------------------------------------------------------------------
--
-- FUNCTION NAME : vhfn (vector high for natural)
--
-- DESCRIPTION : This function returns the 'high value to be used
-- in the range declaration of a vector used to
-- represent the natural value passed to it.
--
-- WARNING: This function assumes the rest of the
-- range declaration of the vector
-- will be "downto 0"
--
-- NOTES : see vlfn for more information
--
-- EXAMPLE :
------------------------------------------------------------------------------
function vhfn(natVal : natural) return natural is
begin
return vlfn(natVal) - 1;
end vhfn;


------------------------------------------------------------------------------
--
-- FUNCTION NAME : vlfi (vector length for integer)
--
-- DESCRIPTION : This function returns an integer representing the
-- length of the vector required to represent
-- the integer value passed to it. This includes
-- the sign bit; hence the "resultVar := loopVar + 1;"
--
-- NOTES : type integer is range -2147483648 to 2147483647;
-- This function can be used in code intended for synthesis
-- Using a 31 bit variable strips off the sign bit that
-- the conversion function generates. This allows us
-- to place the sign bit in the new location at the top
-- of the vector.
--
-- EXAMPLE : -2147483648 passed, convertion to logic vector gives
-- 0000000000000000000000000000000. Bit 31 is '0' and
-- a sign bit is needed so 31 + 1 = 32 bits are needed to
-- represent this value
--
-- given intVal = 32
-- slvVar is assigned 0000000000000000000000000100000
-- "if" condition becomes true for loopVar = 6
-- result is 7 (6 bits to represent 32, plus the sign bit)
------------------------------------------------------------------------------
function vlfi(intVal : integer) return natural is
variable loopVar : natural;
variable resultVar : natural;
variable slvVar : std_logic_vector(31 downto 1); -- range of 31 downto 1 used because the numbering is correct for the positional location of the bits
begin
slvVar := conv_std_logic_vector(intVal,slvVar'length); -- convert the integer passed to the function to a 31 bit logic vector
if (intVal > 0) then -- if the integer is positive then
for loopVar in slvVar'range loop -- start at the top of the vector and index down
if (slvVar(loopVar) = '1') then -- and if a bit is asserted then
resultVar := loopVar + 1; -- this is the minimum number of bits needed to represent the absolute value. And then add one for the sign bit
exit;
end if;
end loop;
elsif (intVal = 0) then -- '0' has no value and, therefore, needs no sign bit
resultVar := 1;
elsif (intVal = -1) then -- '-1' is a special case which contains no zeros so the following algorithm would fail.
resultVar := 2;
elsif (intVal < -1) then -- if the integer is negative then
for loopVar in slvVar'range loop -- start at the top of the vector and index down
if (slvVar(loopVar) = '0') then -- and if a bit is asserted then
resultVar := loopVar + 1; -- this is the minimum number of bits needed to represent the absolute value. And then add one for the sign bit
exit;
end if;
end loop;
end if;
return resultVar;
end vlfi;


------------------------------------------------------------------------------
--
-- FUNCTION NAME : vlfn (vector length for natural)
--
-- DESCRIPTION : This function returns an integer representing the
-- length of the vector required to represent
-- the natural value passed to it. There is no
-- sign bit needed so "resultVar := loopVar;"
--
-- NOTES : subtype natural is integer range 0 to integer'high;
-- This function can be used in code intended for synthesis
--
-- EXAMPLE : given natVal = 32
-- slvVar is assigned 0000000000000000000000000100000
-- "if" condition becomes true for loopVar = 6
-- result is 6 (6 bits to represent 32, no sign bit needed)
------------------------------------------------------------------------------
function vlfn(natVal : natural) return natural is
variable loopVar : natural;
variable resultVar : natural;
variable slvVar : std_logic_vector(31 downto 1);
begin
slvVar := conv_std_logic_vector(natVal,slvVar'length);
if (natVal > (2**31 - 1)) then
assert false
report "value exceeds 2**32-1 (2147483647)"
severity warning;
elsif (natVal > 0) then
for loopVar in slvVar'range loop
if (slvVar(loopVar) = '1') then
resultVar := loopVar;
exit;
end if;
end loop;
else
resultVar := 1;
end if;
return resultVar;
end vlfn;


------------------------------------------------------------------------------
--
-- FUNCTION NAME : vrfi (vector range for integer)
--
-- DESCRIPTION : This function returns a std_logic_vector of the same range
-- required to represent the integer value passed to it.
-- This includes the sign bit;
--
-- NOTES : subtype natural is integer range 0 to integer'high;
-- This function can be used in code intended for synthesis
--
------------------------------------------------------------------------------
function vrfi(intVal : integer) return std_logic_vector is
variable slvVar : std_logic_vector(vhfi(intVal) downto 0);
attribute int_slv_range : natural;
attribute int_slv_range of slvVar : variable is slvVar'range;
begin
return slvVar;
end vrfi;


--------------------------------------------------------------------------------
----
---- FUNCTION NAME : vrfi (vector range for integer)
----
---- DESCRIPTION : This function returns a std_logic_vector of the same range
---- required to represent the integer value passed to it.
---- This includes the sign bit;
---- hence the "resultVar := loopVar + 1;"
----
---- NOTES : subtype natural is integer range 0 to integer'high;
---- This function cannot be used in code intended for synthesis
----
--------------------------------------------------------------------------------
---- synopsys translate_off
--function vrfi(intVal : integer) return std_logic_vector is
-- type slv_ptr is access std_logic_vector;
-- variable size : slv_ptr;
-- variable loopVar : natural;
-- variable resultVar : natural;
-- variable slvVar : std_logic_vector(31 downto 1);
--begin
-- slvVar := conv_std_logic_vector(intVal,slvVar'length); -- convert the integer passed to the function to a 31 bit logic vector
-- if (intVal > 0) then -- if the integer is positive then
-- for loopVar in slvVar'range loop -- start at the top of the vector and index down
-- if (slvVar(loopVar) = '1') then -- and if a bit is asserted then
-- resultVar := loopVar + 1; -- this is the minimum number of bits needed to represent the absolute value. And then add one for the sign bit
-- exit;
-- end if;
-- end loop;
-- elsif (intVal = 0) then -- '0' has no value and, therefore, needs no sign bit
-- resultVar := 1;
-- elsif (intVal = -1) then -- '-1' is a special case which contains no zeros so the following algorithm would fail.
-- resultVar := 2;
-- elsif (intVal < -1) then -- if the integer is negative then
-- for loopVar in slvVar'range loop -- start at the top of the vector and index down
-- if (slvVar(loopVar) = '0') then -- and if a bit is asserted then
-- resultVar := loopVar + 1; -- this is the minimum number of bits needed to represent the absolute value. And then add one for the sign bit
-- exit;
-- end if;
-- end loop;
-- end if;
-- size := new std_logic_vector(resultVar-1 downto 0);
---- return size.all'range;
-- return size.all;
-- deallocate(size);
--end vrfi;
---- synopsys translate_on


------------------------------------------------------------------------------
--
-- FUNCTION NAME : vrfn (vector range for natural)
--
-- DESCRIPTION : This function returns an std_logic_vector representing the
-- length of the vector required to represent
-- the natural value passed to it.
--
-- NOTES : subtype natural is integer range 0 to integer'high;
-- This function can be used in code intended for synthesis
--
------------------------------------------------------------------------------
function vrfn(natVal : natural) return std_logic_vector is
variable slvVar : std_logic_vector(vhfn(natVal) downto 0);
begin
return slvVar;
end vrfn;


--------------------------------------------------------------------------------
----
---- FUNCTION NAME : vrfn (vector range for natural)
----
---- DESCRIPTION : This function returns an std_logic_vector representing the
---- length of the vector required to represent
---- the natural value passed to it.
----
---- NOTES : subtype natural is integer range 0 to integer'high;
---- This function cannot be used in code intended for synthesis
----
--------------------------------------------------------------------------------
---- synopsys translate_off
--function vrfn(natVal : natural) return std_logic_vector is
-- type slv_ptr is access std_logic_vector;
-- variable size : slv_ptr;
-- variable loopVar : natural;
-- variable resultVar : natural;
-- variable slvVar : std_logic_vector(31 downto 1);
--begin
-- slvVar := conv_std_logic_vector(natVal,slvVar'length);
-- if (natVal > 0) then
-- for loopVar in slvVar'range loop
-- if (slvVar(loopVar) = '1') then
-- resultVar := loopVar;
-- exit;
-- end if;
-- end loop;
-- else
-- resultVar := 1;
-- end if;
-- size := new std_logic_vector(resultVar-1 downto 0);
-- return size.all;
-- deallocate(size);
--end vrfn;
---- synopsys translate_on











------------------------------------------------------------------------------
--
-- Procedures
--
------------------------------------------------------------------------------


------------------------------------------------------------------------------
--
-- FUNCTION NAME : countdown_from
--
-- DESCRIPTION : counts down from a time value
--
-- NOTES : synthesizeable
--
------------------------------------------------------------------------------
procedure countdown_from(
signal timeVal : in time;
signal freqVal : in frequency;
signal enableIn : in std_logic;
signal count_RIn : in std_logic_vector;
signal count_Out : out std_logic_vector
) is
begin
count_Out <= count_RIn;
if (count_RIn(count_RIn'high) = '1') then
count_Out <= time_to_slv(timeVal-2*to_period(freqVal),freqVal);
elsif (enableIn = '1') then
count_Out <= count_RIn - '1';
end if;
end countdown_from;


------------------------------------------------------------------------------
--
-- FUNCTION NAME : FF
--
-- DESCRIPTION : simple flip flop procedure
--
-- NOTES : synthesizeable
--
------------------------------------------------------------------------------
procedure FF
(
signal Clk : in std_logic;
signal Rst : in std_logic;
signal D : in std_logic_vector;
signal Q : out std_logic_vector
) is
variable zeros : std_logic_vector(Q'range) := (others => '0');
begin
if (Rst = '1') then
Q <= zeros;
elsif Rising_Edge(Clk) then
Q <= D;
end if;
end FF;


------------------------------------------------------------------------------
--
-- FUNCTION NAME : slv_to_bcd
--
-- DESCRIPTION : This function converts an unsigned, decending range,
-- binary value into a packed binary coded decimal (BCD)
-- standard logic vector and returns the result in
-- the number BCD digits required to represent the maximum
-- unsigned value possible in the vector passed to it.
-- it is for use in pipelined implementations where
-- the binary coded decimal output is registered
-- and passed back to the function along with the binary
-- vector input to be shifted out of its MSB
-- register and into the function as a new bit.
--
--
-- NOTES
-- BCD_DigitsVal -> dpfslvr(vectorVal)
------------------------------------------------------------------------------
procedure slv_to_bcd(
signal BCD_RIn : in std_logic_vector;
signal BinIn : in std_logic_vector;
signal BinFBIn : in std_logic_vector;
signal ClkIn : in std_logic;
constant BCD_DigitsVal : in integer;
signal EnIn : in std_logic;
signal RstLowIn : in std_logic;
signal BCD_ROut : out std_logic_vector;
signal Bin_ROut : out std_logic_vector; -- registed, shifted version of BinIn
signal DoneOut : out std_logic) is
constant BCD_ZEROS : std_logic_vector(BCD_ROut'range) := (others => '0');
constant BIN_ZEROS : std_logic_vector(BinIn'range) := (others => '0');
variable BCD_Var : std_logic_vector(BCD_ROut'range);
variable BCD_RVar : std_logic_vector(BCD_ROut'range);
begin
if (RstLowIn = '0' or EnIn = '0') then
BCD_ROut <= BCD_ZEROS;
BCD_RVar := BIN_ZEROS;
Bin_ROut <= BinIn;
DoneOut <= '0';
elsif rising_edge(ClkIn) then
Bin_ROut <= BinFBIn(BinFBIn'high-1 downto BinFBIn'low) & '0';
if (BinFBIn = BIN_ZEROS) then
BCD_ROut <= BCD_RIn;
DoneOut <= '1';
else
BCD_ROut <= slv_to_bcd_pipe(BCD_RIn,BinFBIn(BinFBIn'high),BCD_DigitsVal);
DoneOut <= '0';
end if;
end if;
end slv_to_bcd;