Help in writing synthesizable code??

[dcreddy1980]

entity test is
port(X : in std_logic;
clk : in std_logic;
Y : out std_logic);
end test;

architecture behaviour of test is
signal tmp : integer :=3;
constant clock period : time := 2 ns;
begin
Y <= X after tmp * clock period; -- "X after 6 ns"
end behaviour;

can body give me some ideas in synthesizing the above code...especially i
want to remove the statement "X after tmp*clock period".

Regards,
chaitanya

 

[Nicolas Matringe]

dcreddy1980 a écrit:

entity test is
port(X : in std_logic;
clk : in std_logic;
Y : out std_logic);
end test;

architecture behaviour of test is
signal tmp : integer :=3;
constant clock period : time := 2 ns;
begin
Y <= X after tmp * clock period; -- "X after 6 ns"
end behaviour;

can body give me some ideas in synthesizing the above code...especially i
want to remove the statement "X after tmp*clock period".

'after' clause is not synthesizable.
If you want to delay your input signal by a number of clock periods, you
have to use a delay chain:

architecture rtl of test is
constant tmp : natural := 3;
begin
process (clk)
variable chain : std_logic_vector(tmp - 1 downto 0);
begin
if rising_edge(clk) then
chain := chain(chain'left - 1 downto 0) & X;
Y <= chain(chain'left);
end if;
end process;
end rtl;

 

[bxbxb3]

u can also use state machines with no. of states=6. assign y<=x in state 6
and y<=y for the rest of states.